vlsidesignshift1
Newbie level 2
I have written a code for GF(16) multiplier in XILINX but i am getting some errors.plz help me.
THE above code is correct and i even got the required output but i am getting error in the next code which i wrote for polynomial reducer.
CODE:
THE error i got was
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 module mult4_4( input [3:0]a, input [3:0]b, output p0,p1,p2,p3,p4,p5,p6,p7 ); wire[15:0]w; wire[5:0]s; wire[10:0]c; and(w[0],a[0],b[0]); and(w[1],a[1],b[0]); and(w[2],a[2],b[0]); and(w[3],a[3],b[0]); and(w[4],a[0],b[1]); and(w[5],a[1],b[1]); and(w[6],a[2],b[1]); and(w[7],a[3],b[1]); and(w[8],a[0],b[2]); and(w[9],a[1],b[2]); and(w[10],a[2],b[2]); and(w[11],a[3],b[2]); and(w[12],a[0],b[3]); and(w[13],a[1],b[3]); and(w[14],a[2],b[3]); and(w[15],a[3],b[3]); HA HA1(w[5],w[8],s[0],c[0]); HA HA2(w[9],w[12],s[1],c[1]); HA HA3(w[10],w[13],s[2],c[2]); FA FA1(w[6],w[3],s[1],s[3],c[3]); FA FA2(c[1],w[7],s[2],s[4],c[4]); FA FA3(w[11],w[14],c[2],s[5],c[5]); assign p0=w[0]; HA HA4(w[1],w[4],p1,c[6]); FA FA4(w[2],s[0],c[6],p2,c[7]); FA FA5(s[3],c[0],c[7],p3,c[8]); FA FA6(s[4],c[3],c[8],p4,c[9]); FA FA7(s[5],c[4],c[9],p5,c[10]); FA FA8(w[15],c[5],c[10],p6,p7); endmodule
THE above code is correct and i even got the required output but i am getting error in the next code which i wrote for polynomial reducer.
CODE:
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 module MUL(x,p0,p1,p2,p3,p4,p5,p6,p7); input p0,p1,p2,p3,p4,p5,p6,p7; output [3:0]x; mult4_4 MUL1(.p0(p0),.p1(p1),.p2(p2),.p3(p3),.p4(p4),.p5(p5),.p6(p6),.p7(p7)); assign x[0]=p0^p4; assign x[1]=p1^p5^p4; assign x[2]=p2^p6^p5; assign x[3]=p3^p6; endmodule
THE error i got was
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