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Matching network of power amplifier design in cadence

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jigao

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Hello,

I am designing a power amplifier in cadence, but I don't know how to design matching network in cadence. I found that some papers solve this by hand calculating but deviation of this method is too large.
I'd like to know whether I can design the matching network in cadence like in the ADS ? (I don't have the pdk document which is fit for ADS)

Many thanks.
 

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