Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

PRBS output values vhdl

Status
Not open for further replies.
K

Kosyas41

Member level 3
Joined
Apr 12, 2016
Messages
62
Helped
0
Reputation
0
Reaction score
0
Trophy points
6
Activity points
502
Hello,
Could you pls give me some hints about PRBS code.My code is working fine.but I would like to modify it. I want that output value will change at leasr after 100ps.
Code: 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity random is
    generic ( width : integer :=  5000 ); 
port (
      clock : in std_logic;
      random_num : out std_logic   --output vector            
    );
end random;

architecture random_arch of random is
begin
process(clock)
variable rand_temp : std_logic_vector(width-1 downto 0):=(width-1 => '1',others => '0');
variable temp : std_logic := '0';
begin
if clock'event and clock = '0' then
temp := rand_temp(width-1) xor rand_temp(width-2);
rand_temp(width-1 downto 1) := rand_temp(width-2 downto 0);
rand_temp(120) := temp;
end if;
random_num <= rand_temp(960);
end process;
end;
 
Last edited:

It might be helpful to be more specific about what it is you need to better understand and where you are heading with the modifications.
 
My PRBS feeds data to psk modulator. in tb for modulator input signal changing with long period and I can observe correct picture today. When I connect PRBS and modulator, input signal (1 and 0) changing quite fast and thats why modulator not able to modulate it. I want to modify my code next. Output data from PRBS changing not so fast as now, for example value 1 has duration at least 100ps.
 

I'm not sure how familiar you are with VHDL or logic design but if your psk modulator requires data input every so many clocks then it would usually have some sort of data write enable input (normally set to logic '1' for 1 clock cycle for a data write).
This same signal should be used to enable this module when required.

I would normally do something like this....

Code: 
entity random is
generic
(
    width : integer :=  5000
); 
port
(
    clock            : in std_logic;
    enable          : in std_logic;
   random_num : out std_logic   --output vector            
);
end random;

architecture random_arch of random is
begin

process(clock)
....
....
if rising_edge(clock) then
    if enable = '1' then
....
....
....
....
....
    end if;
end if;
end process;
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top