icc read verilog problem

Hi,

I am using ic compiler an during read verilog i am getting an issue.

the error report is

import_designs -format verilog -top ChipTop -cel ChipTop {../../dc/output/compile.v}
Warning: /home/training/my_pnr/icc/ref/SAED32_2012-12-25/lib/stdcell_rvt/milkyway/saed32nm_rvt_1p9m: bus naming style _<%d> is not consistent with main lib. (MWNL-111)

***** Verilog HDL translation! *****

***** Start Pass 1 *****
Compiling source file /home/training/my_pnr/lpmm_labs_12-16-2015/lpmm32_lab_data/multi_voltage/dc/output/compile.v

***** Pass 1 Complete *****
Elapsed = 0:00:02, CPU = 0:00:01

***** Verilog HDL translation! *****

***** Start Pass 2 *****
Compiling source file /home/training/my_pnr/lpmm_labs_12-16-2015/lpmm32_lab_data/multi_voltage/dc/output/compile.v
Error: /home/training/my_pnr/lpmm_labs_12-16-2015/lpmm32_lab_data/multi_voltage/dc/output/compile.v:413: module DFFSSRX1_RVT is not defined.
(VER-500)
Error: Module 'DFFSSRX1_RVT' is not defined. (MWNL-297)
Error: /home/training/my_pnr/lpmm_labs_12-16-2015/lpmm32_lab_data/multi_voltage/dc/output/compile.v:413: ERROR: near line 413: Port connection failed.
(VER-500)

Error: Verilog parser cannot parse the /home/training/my_pnr/lpmm_labs_12-16-2015/lpmm32_lab_data/multi_voltage/dc/output/compile.v source file. (MWNL-047)
1

I am complete milkyway databse an read all the libs.

Please help.

You can manually check this cell "DFFSSRX1_RVT" has been read or not ?
The log showed that the compiler could not find its module.

I'm guessing that the Verilog file, {../../dc/output/compile.v}, does not list the definition of the module, DFFSSRX1_RVT.
You would have to locate the definition of that module append/include that in compile.v.
The module definition would eventually lead ICC to initialize that "_RVT" design as a collection of gates and nets.