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MOSFET dv/dt, how does it apply?

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Hi.

My understanding thus far is that in MOSFET datasheets the maximum dv/dt is specified (generally as a number of volts per ns).

I read somewhere that this applies to the rising of the voltage between the D and S (eg when the MOSFET turns off). EG your actual rising edge signal must be slower than the spec to prevent MOSFET failure. Is this correct?

Does anything apply to the MOSFET turn on (falling of voltage between D and S)?

Cheers.
 

During rising edge transition of the voltage accross Drain and Source, the higher dv/dt, the higher peak current accross the intrinsic capacitance Cdg, which in certain way performs a negative feedback, which tends to keep the Mosfet in the ohmic region for more time, increasing the switching heating.
 
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    CataM

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Beyond that, drain dV/dt couples displacement charge
(of the Cdb capacitance) into the body potentially
turning on the parasitic NPN (D-B-S) BJT with a high
potential for loss of control or catastrophic damage
(as conduction may not be uniform, BJTs being prone
to current hogging and hot-spotting as Vbe and shunt
Rbe both have unfortunate tempcos).
 

Hi,

I can´t remember that there is a dV/dt limit that you don´t have to exceed with Mosfets.

I can imagine two things:
* for the (slow) recovery body diode
* or that the dV/dt given in the datasheet gives the max expectabe rise/fall rate with a specified gate drive current.

--> Please give a link to a datasheet where you find the dV/dt limitation.
(I expect there is an explanation)

Klaus
 

dV/dt limit values can be found for most high voltage MOSFET. Besides a rating for gate controlled turn-off, there can be a lower limit value for commutation speed of body diode. It's particularly critical in possibly turning on a parasitic BJT and destroying the MOSFET.

I don't see a reason for a turn-on dV/dt limit.

--> Please give a link to a datasheet where you find the dV/dt limitation.
(I expect there is an explanation)
Click to expand...
See many HV MOSFET datasheets (e.g. from Infineon, ST). There's usually no explanation in the datasheet.
 

KlausST said:
Hi,

It seems dV/dt is a problem for the body diode.

Here an application note I found:
https://www.infineon.com/dgdl/Infineon - Application Note - Power MOSFETs - OptiMOS 200V 250V.pdf

Klaus
Click to expand...

Sorry but your link doesn't work for me....

- - - Updated - - -

Ok

Ok. I have found another useful resource on this.....

https://www.infineon.com/dgdl/mosfet.pdf?fileId=5546d462533600a4015357444e913f4f
PG11 onwards.

I have never investigated this dv/dt spec before but I am working on a high frequency flyback convertor and chose this FET for its very low capacitances.
I my Vds rising edge is so sharp that I am badly over max rating (spec is 4.5V/ns) I am seeing a 100V rise in 14ns!!
 

Checking some other datasheets again, it does appear to be two separate parameters. Its just that some datasheets list one, some the other, some both, some neither.

There seams to be a consistent theme of about 50V/ns for the active dv/dt and 4 - 5ns for the diode.

For me this begs the question, is there a situation where we don't need to make sure our circuit is slower than the slowest of these ratings?

Referring back to that document I posted the link to, I'm guessing that the active dv/dt limit is due to the gate-drain capacitance and the diode limit is due to the parasitic transistor (formed by the body diode.).
 

Not all MOSFET circuits will cause body diode conduction and respectively don't need to care for reverse recovery. E.g. a typical single transistor flyback or boost PFC converter.
 

I totally understand what you are saying about the reverse diode not conducting in, say, a flyback circuit but for me its not clear that this diode dv/dt only applies if the diode has been conducting.

Are you saying that this spec only applies during reverse recovery time?
 

dick_freebird said:
Beyond that, drain dV/dt couples displacement charge
(of the Cdb capacitance) into the body potentially
turning on the parasitic NPN (D-B-S) BJT with a high
potential for loss of control or catastrophic damage
...
Click to expand...
FvM said:
It's particularly critical in possibly turning on a parasitic BJT and destroying the MOSFET.
Click to expand...

Shorting the body to the source supresses the parasitic NPN transistor and only leaves space for the PN body diode.

Quote from Power MOSFETs by TI, page 4 Parasitic body diode
Early versions of MOSFETs were very susceptible to voltage breakdown due to voltage transients and also had a
tendency to turn on under high rates of rise of drain-to source voltage (dV/dt), both resulting in catastrophic failures.
The dV/dt turn-on was due to the inherent parasitic NPN transistor incorporated within the MOSFET, shown
schematically in Figure 4a . Current flow needed to charge up junction capacitance CDG acts like base current to turn
on the parasitic NPN.
The parasitic NPN action is suppressed by shorting the N+ source to the P+ body using the source metallization. This
now creates an inherent PN diode in anti-parallel to the
MOSFET transistor (see Figure 4b ).
Click to expand...
 

CataM said:
Shorting the body to the source supresses the parasitic NPN transistor and only leaves space for the PN body diode.
Click to expand...

That's a lovely theory, but there is no perfect short
and the placement of body contacts steals explicit
channel width (in a cellular style) while in a stripe
style the body contact is on the other side of the
source, than the neck / drain path so sees the
pinched body resistance. In any case the shorting
at the topside is not the feature of interest. It's
the subsurface neck region (the BJT base) between
source (E) and drain (C) and always there's an
access resistance through the P-neck (and by its
design the neck operates close to pinchoff).

Commercial power MOSFETs are a cut-throat pricing
segment, sales come from Ron*BVdss/$$$, $$$ being
largely die area and die area encompassing the S, B
contacts, the neck and the drain-drop. Cheap FETs
are likely to optimize simple Ron*BVdss @ $$$ and leave
the dV/dt tolerance to up-market products that have
users who care enough to sacrifice either Ron or $$$.
 
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    CataM

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Hi!

If your MOSFET's gate is pulled down with a big value resistor (for example, 10k-100k Ohms) and if you have very large dV/dt value, a current begins to flow through the Miller capacitance (between drain and gate) and through this PD resistor on the ground with value
\[I = C\frac{\mathrm{d}V}{\mathrm{d} t}\]
It causes the IR-drop on your PD resistor, and MOSFET opens spontaneously.

Grigorii
 

Gregor812 said:
If your MOSFET's gate is pulled down with a big value resistor (for example, 10k-100k Ohms) and if you have very large dV/dt value, a current begins to flow through the Miller capacitance (between drain and gate) and through this PD resistor on the ground with value
Click to expand...

In general, the gate series resistor from the driver, which lies in the maximum range of few dozens ohms, is were more attention is concerned on designs. It should be not too high to avoid the parasitic turn-on of the Mosfet during the cut-off switching, but not too low to avoid inrush a high peak current from driver to gate.
 

for me its not clear that this diode dv/dt only applies if the diode has been conducting.

Are you saying that this spec only applies during reverse recovery time?
Click to expand...
dV/dt limit values are usually only a problem for MOSFETs in push-pull circuits, where the rising Vds edge is actively driven by another switch. This is the case e.g. in hard switching half- and full bridges. Depending on the operation quadrant and switch timing, body diode reverse recovery may be involved or not.

If the rising Vds edge occurs under reverse recovery conditions (with charge carriers stored in the body diode junction), a lower dV/dt rate must be observed to avoid triggering of the parasitic BJT.

As said, dV/dt can be controlled by reducing the turn-on gate current for the "opposite" transistor causing the rising edge. Asymmetrical slow turn-on, fast turn-off gate circuits are a common solution to achieve this without affecting turn-off speed and risking shoot-trough.
 
Thanks FvM, you say that with enough conviction to convince me.

I'm working on more than one design right now (different topologies) but the main one is a flyback with the following specs:
1MHz sw freq
Vin 48V
Vout 12V
Power out 10-20W

I have chosen a FET with very low output capacitances and getting dv/dt (Vds) values of about 7.1V/ns rising and 32V/ns on falling. Gives you some idea why I'm asking the questions.....
 

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