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    [Moved]: Question regarding Veff and IC

    Hi everyone,

    I have a question regarding Veff.

    I am reading Binkley's book and he defines as VEFF = VGS-VT, meaning, represents how much the operating gate-source voltage is above (positive) or below (negative) the mosfet threshold voltage.

    If we look at the plot of figure 3.3 in his book, we see that he has at IC=1, a VEFF = 40mV, at IC=0.1, a VEFF = -72mV and at IC=10, a VEFF = 225mV.

    This means that each of this VEFF are above the threshold voltage PLUS the threshold voltage, right? The gate voltage is biased 40mV above the threshold voltage which makes it be in the moderate inversion. Right?

    Now, this threshold voltage, VT, that he's referring to is the normal VT voltage from the MOSFET (which will include all the second order effects) or it is the VT0 (with VSB=0V)?

    I would like to make the same plot as he, for my technology, that's why I wanted to know if the VT that he's referring too is the VT0 or the normal VT that we are used to, so that I can bias correctly the transistor.

    Regards.
    Last edited by erikl; 16th January 2017 at 16:49. Reason: Establishing old title

    •   Alt12th January 2017, 11:24

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    Technology Current dependency on Gate-Length

    Dear @erikl,

    Let me take the advantage of this post to make a question about something that I have forgotten, regarding the technology current, I0, and that is linked with the inversion coefficient, IC.

    The way Binkley derive this current, which can be seen in his book, is model independent?

    My question:
    According to Binkley his technology current is fixed, in this case around 0.64uA. How the simulation that we are doing gives different values of I0 for each W=L?

    Your answer:
    If you had read/studied the Binkley - or any other Analog Circuit Design - book thoroughly, you'd know the answer: short channel effects as carrier velocity saturation (mobility reduction due to the longitudinal field), CLM and VFMR throttle (pinch, reduce) the drain current most at Lmin, and less and less at longer channel lengths. That's why you get a low I0 value at Lmin and some higher, but more and more saturating I0 values for longer channel lengths.
    erikl, I would like to clarify something. I had to read two or three times you answer and my question

    I know all the things that you mentioned on your answer. But what I meant to ask is the following:

    If you look at Binkley results and informations in the book, starting for example on page 43 (table 3.2), you can see that his technology current is 0.64uA and it was calculated based on the I0 expression and his technology parameters.

    As you can see, this current doesn't depend on the W/L ratio and he uses this I0 current throughout his examples, as you can see in some tables or plots.

    One example of this is on page 63, figure 3.7. This plot exercise is using the I0 of 0.64uA and it has in its x-axis the IC which depends as well on I0.

    What is confusing me is the fact that when we simulate, we are using different values of W, with W/L=1. This gives different values of currents.

    Now when Binkley says for a certain plot or whatever that the technology current is 0.64uA, W/L=1 etc, etc, how do we know which value of W, and consequently the value of L, he used? Do you understand what I mean? Please, if you didn't understand tell me to try another way.

    Please, I am looking forward to hear from you. I will be waiting for you answer as this piece of information is very important to me.

    Thank you for you time and availability.
    Regards.



    •   Alt13th January 2017, 17:43

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  3. #3
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    Re: Technology Current dependency on Gate Length

    Quote Originally Posted by CAMALEAO View Post
    ... regarding the technology current, I0 ...
    The way Binkley derive this current, which can be seen in his book, is model independent?
    The way, yes. But the results of course not. Different models contain different model parameters.

    Quote Originally Posted by CAMALEAO View Post
    If you look at Binkley results and informations in the book, starting for example on page 43 (table 3.2), you can see that his technology current is 0.64uA and it was calculated based on the I0 expression and his technology parameters.
    Correct: it was calculated. But from physical values only!

    Quote Originally Posted by CAMALEAO View Post
    As you can see, this current doesn't depend on the W/L ratio and he uses this I0 current throughout his examples, as you can see in some tables or plots.
    Right. It can't depend on W/L, because this value doesn't appear in the equation.


    Quote Originally Posted by CAMALEAO View Post
    What is confusing me is the fact that when we simulate, we are using different values of W, with W/L=1. This gives different values of currents.
    This is the difference between theory and praxis. For designing (practical) analog IC circuits we need transistors with differing gate lengths L. And in practice, for transistors with different L's arise differing I0 values, as e.g. can be seen in my figure: Attachment 135050
    which have been simulated with W/L=1 transistors.

    BTW: You'd also get differing I0 values from the physical equation
    technology_current.png
    ... if you'd consider the differing µ values depending on L .


    Quote Originally Posted by CAMALEAO View Post
    Now when Binkley says for a certain plot or whatever that the technology current is 0.64uA, W/L=1 etc, etc, how do we know which value of W, and consequently the value of L, he used?
    We can't know, because there's neither W nor L nor W/L in his equation, so he didn't use them at all. His I0 value is a theoretical value, purely based upon physical material values!

    Quote Originally Posted by CAMALEAO View Post
    Do you understand what I mean?
    I hope I do. And I hope you may understand my explanations.



    •   Alt16th January 2017, 16:09

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    Re: [Moved]: Question regarding Veff and IC

    Hi erikl,
    Thanks for replying to my post. I want to let you that I do understand your explanations and I don’t have anything against your answers. However, sometimes I think you might not understand what I mean.

    The explanations that you gave although it was clear still not answer to my doubt. However, let me try another approach. If you grab Binkley’s paper: Tradeoffs and optimisation in Analog CMOS design, which I believe its content is available in the book, but using the paper is more straightforward and easy to understand, you can see an example of an amplifier. If you go to table 1, you will see the basic parameters from his technology including the technology current, which has the same value as in his book, 0.64uA.

    If you go to page 55 and look at the amplifier (fig. 11), you will see that some of the transistors have different lengths. So things to keep in mind: one technology current and different lengths of the transistors.

    If you calculate for yourself the width of each transistor using the data present in that same figure of the amplifier along with the technology current (0.64uA, calculated) you will get roughly the same results that he got, for different lengths. So things to keep in mind here: calculated technology current, different lengths and IC’s.

    So as you can see he is using the same technology current for different lengths. That’s my main point. So, how come we, through the simulation, use different values of the technology current accordingly to the length of the transistor? It looks like he doesn’t take into account that. The other example, which I think I have given to you, is the one in page 64 of his book, where for different values of lengths he calculates the width of the MOSFET using always the same technology current.

    I am not saying that you are wrong. I am trying to understand why you are doing that way and Binkley is doing that way. If you are using the same approach as him, he should have the same logical approach, different technology currents for different lengths, which is not the case. So I am completely confused.
    Do you understand what I mean?

    Best regards and I am looking forward to continuing this discussion with you.



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    Re: [Moved]: Question regarding Veff and IC

    Dear @erikl, can you comment?

    Regards.



    •   Alt23rd January 2017, 16:41

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    Re: [Moved]: Question regarding Veff and IC

    Quote Originally Posted by CAMALEAO View Post
    ...
    So as you can see he is using the same technology current for different lengths. That’s my main point. So, how come we, through the simulation, use different values of the technology current accordingly to the length of the transistor? It looks like he doesn’t take into account that. The other example, which I think I have given to you, is the one in page 64 of his book, where for different values of lengths he calculates the width of the MOSFET using always the same technology current.

    I am not saying that you are wrong. I am trying to understand why you are doing that way and Binkley is doing that way. If you are using the same approach as him, he should have the same logical approach, different technology currents for different lengths, which is not the case. So I am completely confused.
    Do you understand what I mean?
    I hope so, CAMALEAO.

    Right: Binkley uses a fixed Technology Current (per technological process size) for different gate lengths - whereas I use different Technology Currents for different gate lengths. And you want to know, why. I thought (and hoped) I was clear enough with my reasons which I gave you in some posts in a previous thread - but it wasn't so, obviously. So, give it one more try:

    The crucial point is the decline of the charge carrier mobility from the low field value µ0 at long gate lengths down to the minimum process size gate length mobility due to several high field- aka small geometry effects as velocity saturation at high longitudinal E-field, VFMR (vertical field mobility reduction), and DIBL (drain-induced barrier lowering).

    You know this high-E-field braking behavior of the mobility µ0 directly influences the Technology Current I0: technology_current.png where I read µ instead of µ0, which resulted in this measured technology current I0 vs. channel length L - curve for my 0.18µm process: technology_current_i0_vs_channel_length_l.png.

    Measured from real silicon transistors! So: from experience.

    And why would one need minimum length transistors? It's not usual in Mixed Signal Analog IC Design, is it? There are several reasons:

    • For high W/L ratio transistors in relatively slow amplifiers (Binkley calls them DC OTAs), e.g. in the input stages of differential amplifiers
    • For high W/L ratio transistors in high power output stages (order of tens to hundred(s) of milliAmpčres)
    • For any W/L ratio transistors in RF stages (called AC OTAs in Binkley's book), because of minimum capacitance needs


    Reasons # 1 & 2: Transistor area increases quadratically with gate length (for a fixed W/L ratio). And area costs money. Your boss will kill you when & if your design grows too large , e.g. larger than your necessary compensation cap(s)

    Means: sometimes you really need minimum length transistors. But if you don't consider that mobility will decrease, and if you still use the long-gate-length low-field mobility µ0 resp. its corresponding Technology Current I0, you probably won't achieve the so calculated drain current.

    That's why I use 3 or 4 different Technology Current (TC) values, e.g. for 1Lmin , 2Lmin<L<3Lmin , 3Lmin<L<5Lmin , and L>5Lmin .

    I hope you understand now. My W/L-dependent TC usage results from measurements on real silicon, and from experience with several well-working designs. If you use long-length (say: L ≥ 5Lmin) transistors only, you can well cope with this Binkley's fixed TC value - but I wouldn't advice this for shorter gate lengths.



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