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    Request for hardware test

    Dear All

    Good day to you , I have recently prepared one VHDL code for implementing a digital clock and because I don't have any CPLD IC and its programmer , I wonder if any one can test the below code for me and then feedback to me whether the code is correctly working or not

    List of Material :
    4 seven segments
    2 pushbuttons
    1 switch
    1 cpld / fpga IC
    1 oscillator (default is 50 Mhz, obviously if this input clock changes, some change in the code should be taken so that we can have a true and correct 1 hz output to the internal circuits for counting the clock digits. )
    Due to uploading limitations, I have changed the type of the file to txt so simply copy and paste content of the txt file in your vhdl synthesizer tool and go on.

    I will appreciate if anyone can optimize my code for efficient power consumption and output heating.

    Code VHDL - [expand]
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    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;
     
    entity clockticks is Port (
    set : in  STD_LOGIC;
    clr : in  STD_LOGIC;
    clock :in std_logic;
    BTN0 : in std_logic; ---Adjust Minutes
    BTN1 : in std_logic; ---Adjust Hours
    Seg1 : out std_logic_vector (6 downto 0);
    Seg2 : out std_logic_vector (6 downto 0);
    Seg3 : out std_logic_vector (6 downto 0);
    Seg4 : out std_logic_vector (6 downto 0));
     
    end clockticks;
     
    architecture Behavioral of clockticks is
     
    -- Sec, Min, Hr Signals
     
    signal sec : std_logic_vector(5 downto 0);
    signal Min1Temp1 : std_logic_vector(3 downto 0); 
    signal Min10Temp1: std_logic_vector(2 downto 0);
    signal Hr1Temp1 : std_logic_vector(3 downto 0);
    signal Hr10Temp1 : std_logic_vector(1 downto 0);
    signal Min1Temp2 : std_logic_vector(3 downto 0); 
    signal Min10Temp2: std_logic_vector(2 downto 0);
    signal Hr1Temp2 : std_logic_vector(3 downto 0);
    signal Hr10Temp2 : std_logic_vector(1 downto 0);
     
    -- Main Outputs which will be used to generate 7segment code
     
    signal Hr1 : std_logic_vector(3 downto 0); -- 1's place
    signal Hr10 : std_logic_vector(3 downto 0); -- 10's place
    signal Min1 : std_logic_vector(3 downto 0); -- 1's place
    signal Min10 : std_logic_vector(3 downto 0); -- 10's place
     
    -- Clock Division signals
     
    signal temporal: STD_LOGIC;
    signal counter : integer range 0 to 25000000 := 0; -- Producing 1hz out of 50 Mhz oscillator
    signal clk : STD_LOGIC;
     
    begin
     
    -- Producing 1hz clock
     
    process (clr, clock) begin
            if (clr = '1') then
                temporal <= '0';
                counter <= 0;
            elsif rising_edge(clock) then
                if (counter = 25000000) then
                    temporal <= NOT(temporal);
                    counter <= 0;
                else
                    counter <= counter + 1;
                end if;
            end if;
        end process;
    clk <= temporal;
     
    --Digital clock in VHDL
    process(clr, BTN0, set, clk ) --period of clk is 1 second.BTN0
    begin
    if clr = '1' then
      Min1Temp1 <= "0000";
      Min10Temp1 <= "000";
     elsif set ='1' and (rising_edge(clk)) then
      if BTN0 = '0' then 
       if Min1Temp1 < 9 then
       Min1Temp1 <= Min1Temp1 + 1;
       else
       Min1Temp1 <= "0000";
       if Min10Temp1 < 5 then
        Min10Temp1 <= Min10Temp1 + 1;
       else
        Min10Temp1 <= "000";
       end if;
       end if;
      end if;
     end if;
    end process;
    process(clr, BTN1, set, clk ) --period of clk is 1 second.BTN1
    begin
    if clr = '1' then
      Hr1Temp1 <= "0000";
      Hr10Temp1 <= "00";
     elsif set ='1' then
      if BTN1 = '0' and (rising_edge(clk)) then
      if Hr1Temp1 < 9   then
       if Hr1Temp1 = 3 and Hr10Temp1 = 2 then
        Hr1temp1 <= "0000";  Hr10Temp1 <= "00";
        else
        Hr1Temp1 <= Hr1Temp1 + 1;
        end if;
       else
        Hr1Temp1 <= "0000";
         if Hr10Temp1 < 2 then
         Hr10Temp1 <= Hr10Temp1 + 1;
         else
         Hr10Temp1 <= "00";
         end if;
        end if;
      end if;
    end if;
    end process;
     
    process(clk , clr )   -- clock
     
    begin
    if clr = '1' then
     sec <= "000000";
     Min1Temp2 <= "0000";
     Min10Temp2 <= "000"; 
     Hr1Temp2 <= "0000";
     Hr10Temp2 <= "00";
    elsif ( BTN0 = '0' or BTN1 = '0') then
     Min1Temp2 <= Min1Temp1;
     Min10Temp2 <= Min10Temp1; 
     Hr1Temp2 <= Hr1Temp1;
     Hr10Temp2 <= Hr10Temp1;
    else
      if   (clk' event and clk ='1') then
       if sec >= 59    then
       if Min1Temp2 < 9 then
        Min1Temp2 <= Min1Temp2 + 1;
       else
        Min1Temp2 <= "0000";
        if Min10Temp2 < 5 then
         Min10Temp2 <= Min10Temp2 + 1;
        else
         Min10Temp2 <= "000";
         if Hr1Temp2 < 9   then
          if Hr1Temp2 = 3 and Hr10Temp2 = 2 then
           Hr1temp2 <= "0000";  Hr10Temp2 <= "00";
          else
           Hr1Temp2 <= Hr1Temp2 + 1;
          end if;
         else
          Hr1Temp2 <= "0000";
          if Hr10Temp2 < 2 then
           Hr10Temp2 <= Hr10Temp2 + 1;
          else
           Hr10Temp2 <= "00";
          end if;
         end if;
        end if;
       end if;
       sec <= "000000";
      else
       sec <= sec + 1;
      end if;
      end if;
    end if;
     
     
    end process;
     
     
     
    Min1 <=  Min1Temp1 when (BTN0 = '0') else  Min1Temp2 when (BTN0 = '1');
    Min10 <= ('0' & Min10Temp1) when (BTN0 = '0') else  ('0' & Min10Temp2) when (BTN0 = '1');
    Hr1  <=  Hr1Temp1 when (BTN1 = '0') else Hr1Temp2 when (BTN1 = '1');
    Hr10 <= ("00" & Hr10Temp1) when (BTN1 = '0') else  ("00" & Hr10Temp2) when (BTN1 = '1');
     
    -- Display on segment 
    process (clk,Min1)
    BEGIN
    if (clk'event and clk='1') then
    case  Min1 is
    when "0000"=> Seg1 <="0000001";  -- '0'
    when "0001"=> Seg1 <="1001111";  -- '1'
    when "0010"=> Seg1 <="0010010";  -- '2'
    when "0011"=> Seg1 <="0000110";  -- '3'
    when "0100"=> Seg1 <="1001100";  -- '4' 
    when "0101"=> Seg1 <="0100100";  -- '5'
    when "0110"=> Seg1 <="0100000";  -- '6'
    when "0111"=> Seg1 <="0001111";  -- '7'
    when "1000"=> Seg1 <="0000000";  -- '8'
    when "1001"=> Seg1 <="0000100";  -- '9'
     --nothing is displayed when a number more than 9 is given as input. 
    when others=> Seg1 <="1111111"; 
    end case;
    end if;
     
    end process;
     
    -- Display on segment 
    process (clk,Min10)
    BEGIN
    if (clk'event and clk='1') then
    case  Min10 is
    when "0000"=> Seg2 <="0000001";  -- '0'
    when "0001"=> Seg2 <="1001111";  -- '1'
    when "0010"=> Seg2 <="0010010";  -- '2'
    when "0011"=> Seg2 <="0000110";  -- '3'
    when "0100"=> Seg2 <="1001100";  -- '4' 
    when "0101"=> Seg2 <="0100100";  -- '5'
     --nothing is displayed when a number more than 5 is given as input. 
    when others=> Seg2 <="1111111"; 
    end case;
    end if;
     
    end process;
     
    -- Display on segment 
    process (clk,Hr1)
    BEGIN
    if (clk'event and clk='1') then
    case  Hr1 is
    when "0000"=> Seg3 <="0000001";  -- '0'
    when "0001"=> Seg3 <="1001111";  -- '1'
    when "0010"=> Seg3 <="0010010";  -- '2'
    when "0011"=> Seg3 <="0000110";  -- '3'
    when "0100"=> Seg3 <="1001100";  -- '4' 
    when "0101"=> Seg3 <="0100100";  -- '5'
    when "0110"=> Seg3 <="0100000";  -- '6'
    when "0111"=> Seg3 <="0001111";  -- '7'
    when "1000"=> Seg3 <="0000000";  -- '8'
    when "1001"=> Seg3 <="0000100";  -- '9'
     --nothing is displayed when a number more than 9 is given as input. 
    when others=> Seg3 <="1111111"; 
    end case;
    end if;
     
    end process;
     
    -- Display on segment 
    process (clk,Hr10)
    BEGIN
    if (clk'event and clk='1') then
    case  Hr10 is
    when "0000"=> Seg4 <="0000001";  -- '0'
    when "0001"=> Seg4 <="1001111";  -- '1'
    when "0010"=> Seg4 <="0010010";  -- '2'
     --nothing is displayed when a number more than 2 is given as input. 
    when others=> Seg4 <="1111111"; 
    end case;
    end if;
     
    end process;
     
    end Behavioral;

    I am looking forward hearing from you soon .

    Best Regards

    Omid
    Last edited by andre_teprom; 11th January 2017 at 11:50. Reason: moved attached code to the body of the post

    •   Alt11th January 2017, 11:43

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    Re: Request for hardware test

    you should do a functional simulation to test your code.

    Quote Originally Posted by omidrey View Post
    Code VHDL - [expand]
    1
    
    elsif set ='1' and (rising_edge(clk)) then
    ... and a timing analysis. Are you sure your code can be implemented in an CPLD (see above)? Consider debouncing your buttons.
    why are you setting your temporary signals assynchronously with your buttons?
    Code VHDL - [expand]
    1
    
    elsif ( BTN0 = '0' or BTN1 = '0') then

    Code VHDL - [expand]
    1
    
    clk <= temporal;
    not a good idea: you are using the signal 'clk' as a clock, but 'temporal' is a register. You should not drive a clock network with logic.



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    Re: Request for hardware test

    for doing functional test I need to write test bench which I dont know how to do , that's why I requested some one do the hardware test for me.

    Why this code cannot be implemented on CPLD? can you explain more? I didn't get what you mean by pointing out my code.

    Those buttons are asynchronous so that if any of the buttons pressed then the output become updated when we have the set switch on .

    Yes for the clock you are right that we should not drive it with logic , then do you have any solution I can solve it ?

    I will appreciate if you have any solutions to your comments so that I can fix it and implement my digital clock.

    Regards



    •   Alt11th January 2017, 17:34

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    Re: Request for hardware test

    Besides what LatticeSemiconductor has mentioned, why are you inconsistent in your use of rising_edge(clk) and (clk'event and clk = '1') for a clock? Use the first the second method considers transitions from Z, X, U, etc => '1' to be valid clock edges, whereas rising_edge(clk) only considers a '0' to '1' transition to be a valid clock edge.

    Quote Originally Posted by omidrey
    Yes for the clock you are right that we should not drive it with logic , then do you have any solution I can solve it ?
    I will appreciate if you have any solutions to your comments so that I can fix it and implement my digital clock.
    The usual method to deal with clock dividing is to run the logic synchronously with the system clock and create a clock enable pulse that only allows the clocking of FFs at the required period.

    I don't think very many CPLDs if any allow for "clock gating" as you've coded below.
    Code:
    elsif set ='1' and (rising_edge(clk)) then
    This code describes an AND gate in the clock path.

    Note, VHDL stands for VHSIC Hardware Description Language, so you should think in terms of what the VHDL describes as hardware, in this case ANDing a signal with the clock implies an AND gate in the clock path.

    - - - Updated - - -

    And invest in the time to learn to write a testbench. I really doubt anyone will be willing to test your code on hardware for free. Everyone who answers questions here are volunteers (i.e. we don't get paid to do this).



    •   Alt11th January 2017, 18:34

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    Re: Request for hardware test

    Quote Originally Posted by ads-ee View Post
    And invest in the time to learn to write a testbench.
    How can one write 246 lines of VHDL and not know how to do a test bench ?

    Furthermore, in my opinion, you have wrote everything on a single architecture like a C code with many many functions which then needs to write e.g. "the display on segment" code 4 times. I think it would be easier to do, understand, find errors etc if you create components and then instantiate them on the top level. You will then check each component (module which integrates the whole design, which is the top) for errors and will be easier to see if something is not working and where.

    - - - Updated - - -

    Also, you need to add a synchronizer for the asynchronous inputs in order to avoid metastability issues



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    Re: Request for hardware test

    Quote Originally Posted by ads-ee View Post
    Besides what LatticeSemiconductor has mentioned, why are you inconsistent in your use of rising_edge(clk) and (clk'event and clk = '1') for a clock? Use the first the second method considers transitions from Z, X, U, etc => '1' to be valid clock edges, whereas rising_edge(clk) only considers a '0' to '1' transition to be a valid clock edge.


    The usual method to deal with clock dividing is to run the logic synchronously with the system clock and create a clock enable pulse that only allows the clocking of FFs at the required period.

    I don't think very many CPLDs if any allow for "clock gating" as you've coded below.
    Code:
    elsif set ='1' and (rising_edge(clk)) then
    This code describes an AND gate in the clock path.

    Note, VHDL stands for VHSIC Hardware Description Language, so you should think in terms of what the VHDL describes as hardware, in this case ANDing a signal with the clock implies an AND gate in the clock path.

    - - - Updated - - -

    And invest in the time to learn to write a testbench. I really doubt anyone will be willing to test your code on hardware for free. Everyone who answers questions here are volunteers (i.e. we don't get paid to do this).
    Dear Sir , thanks for giving me your time to write reply .. in fact I have synthesized this code on ISE 14.7 and it could be successfully synthesized without any error except two warnings related to putting the BTN0 , BTN1 into the sensitivity list of the process function , moreover I have set the XC9500XL in project setting which then after implementing , ISE suggested one of XC9500XL series CPLDs which has 144 pins. Now I dont know if I can trust ISE and transfer this code to the hardware ? Also today I have ordered USB platform programmer for $38 and I plan to buy this XC9500XL CPLD to be able to test my code. what is your suggestion ? Do you think I can get result?

    Yes you are right , you do not get paid, but can you do me a favor and write a test bench for me for free as a new year gift?



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    Re: Request for hardware test

    Quote Originally Posted by CataM View Post
    How can one write 246 lines of VHDL and not know how to do a test bench ?

    Furthermore, in my opinion, you have wrote everything on a single architecture like a C code with many many functions which then needs to write e.g. "the display on segment" code 4 times. I think it would be easier to do, understand, find errors etc if you create components and then instantiate them on the top level. You will then check each component (module which integrates the whole design, which is the top) for errors and will be easier to see if something is not working and where.

    - - - Updated - - -

    Also, you need to add a synchronizer for the asynchronous inputs in order to avoid metastability issues
    Dear Cata , thanks for feedback . Indeed I did not write whole of this code , the main core of this code is related to a weblog called vhdldesign hosted on blogspot and I guess it is for indian engineers. However I have modified and added some parts such as clock division and seven segment displays so that I can make the main code close to my aim. I'm not that expert to write testbench , I know the procedures but did not get result. And because I'm under time limitation for delivering this project to the unviersity as final project of the VHDL course , I thought to myself maybe it's better I implement hardware test to get quicker results.

    anyhow thanks for your suggestions, by the way can you do me a favor and write a test bench for me or test this code on your FPGA/CPLD?

    Regards



    •   Alt11th January 2017, 19:15

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    Re: Request for hardware test

    Now I dont know if I can trust ISE and transfer this code to the hardware ?
    No one ever does a hardware implementation without doing functional verification (i.e. simulation of design by a test-bench).
    In fact learning to write a test-bench is the only 2nd stage after learning to write RTL.

    anyhow thanks for your suggestions, by the way can you do me a favor and write a test bench for me or test this code on your FPGA/CPLD?
    You seem to be new here. This is not how this forum works. Try out yourself, make mistakes, ask questions, show us what you have done, you'll get all the help. No one will give you the code here.

    Yes you are right , you do not get paid, but can you do me a favor and write a test bench for me for free as a new year gift?
    Instead make a new year resolution and learn how to write a test-bench.
    Last edited by dpaul; 11th January 2017 at 21:53.
    Sharing my ideas and knowledge + learning from the experiences of others is what I am looking for.
    Spoon feeding is not my cup of coffee, so I am ready to show you the path, but it is you who has to walk through it!



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    Re: Request for hardware test

    Quote Originally Posted by omidrey View Post
    in fact I have synthesized this code on ISE 14.7 and it could be successfully synthesized without any error except two warnings related to putting the BTN0 , BTN1 into the sensitivity list of the process function , moreover I have set the XC9500XL in project setting which then after implementing
    So what, it synthesizes, a steaming pile of feces still stinks even if you spay Fabreze on it.

    You've got multiple experienced working engineers telling you the same thing...write a testbench, but you don't seem to care to learn what they are telling you.

    Instead...
    Yes you are right , you do not get paid, but can you do me a favor and write a test bench for me for free as a new year gift?
    Free!? you must be daft.



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