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    Analizing a VHDL program code

    Hi there,

    I am new to this forum as well as i am new to VHDL. Teacher gave as a test to do at home and i have struggles with one of the test.
    We got a code and our task is to analyze it and write down the purpose of the Device. We also have to explain the the purpose of parameter s and out_sig, in_sig, mode, clk ports.

    What i see is that we got a D-trigger, but what is the purpose of it in this specific program - i dont understand.
    Obviously, the clk port is for clock, is there any deeper explanation for that?
    In_sig acts like and input signal and out_sig is for output signal, which is controlled by the trigger, right?

    The code is following:

    Code VHDL - [expand]
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    entity Device is
        generic ( s : integer);
        port ( 
            out_sig : out std_logic;
            in_sig : in std_logic_vector(s-1 downto 0);
            mode : in std_logic;
            clk : in std_logic );
    end Device;
     
    architecture Program of Device is
        component DFF is -- DFF is a synchronious D-trigger
            port ( Q : out std_logic;
                   D : in std_logic;
                   Clk : in std_logic );
        end component;  
     
    signal d, q, in_value : std_logic_vector(s-1 downto 0):= (others => '0');
    signal i : integer := 0;
    begin
    in_value <= in_sig;
    out_sig <= q(0);
     
    g1: for i in 0 to s-1 generate
    begin DFF_inst : DFF port map (
        CKJ => clk,
        D => d(i),
        Q => q(i) );
    end generate g1;
     
    process (mode, in_sig, q)
    begin
        if mode= '0' then d<= in_sig;
    else d <= '0'& q(s-1 downto 1);
        end if;
    end process;
    end Program
    Last edited by andre_teprom; 11th January 2017 at 11:12. Reason: added syntax formatting

    •   Alt11th January 2017, 10:56

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    Re: Analizing a VHDL program code

    I'm not expert in HDL, but it seems a little strange in line 32, the assignment of a vector 'in_sig' to a unary signal 'd'. In addition, CKJ wasn't declared anywhere.
    --------------------------------------------------------------------------------------------------
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    Re: Analizing a VHDL program code

    Quote Originally Posted by andre_teprom View Post
    I'm not expert in HDL, but it seems a little strange in line 32, the assignment of a vector 'in_sig' to a unary signal 'd'. In addition, CKJ wasn't declared anywhere.
    "d" is not unary. "d" is std_logic_vector(s-1 downto 0) declared in line 17.

    However, there are some things strange in that code which makes me doubt a teacher gave you that.

    Line 2: generc "s" is not initialized => how long are the std_logic_vectors ?
    Line 20: assignment of in_sig to in_value, but after that, the in_value is not used any more, then, what is its purpose ? NO PURPOSE whatsoever. that line can be errased.
    Line 18: useless, can be errased.
    Last edited by CataM; 11th January 2017 at 15:37.



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    Re: Analizing a VHDL program code

    Quote Originally Posted by andre_teprom View Post
    I'm not expert in HDL, but it seems a little strange in line 32, the assignment of a vector 'in_sig' to a unary signal 'd'. In addition, CKJ wasn't declared anywhere.
    CKJ is a typo note: JKL are next to eacch other on a keyboard.

    The assignment of in_sig is correctly done to the signal d declared as std_logic vector on line 17. It is not unary as you've suggested.

    Other than the typo, there doesn't seen to be anything especially tricky with the code.

    Other than correcting the statements in the reply. I can't give you answers to a test, that would be considered cheating where I reside. If the point of the test is to determine your ability to read and interpret VHDL, then you've proven, by posting this question, that you don't deserve passing marks on this test.

    The only help I can give is to look at each block of statements like the for loop, the process, etc and determine what logic circuit it describes. But I suspect that will be a stretch as this test problem indicates that your teacher probably thinks of VHDL as a programming language. Given that the architecture is called program...I was almost expecting the name of something to be main too.



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    Re: Analizing a VHDL program code

    Here is how your code works.

    You have 2 modes of operation given by the input "mode: in std_logic;"

    When mode = '0' the "out_sig" is exactly the "in_sig(0)" but sychronized with the clk, which means, you load a bus to your "Device" and he outputs the last bit (bit 0) every clock pulse. That is made by the D flip flop.

    When mode = '1', the "out_sig" has the "before last" value of the "q" signal, this is, if "q" is from 10 to 0, the output is the value of q(1). If you start with mode 1 at the very beginning, the output will be alwyas '0'. BUT, after you load the "in_sig" with mode= '0', then you change to mode='1' and the output will be the before last value of "in_sig".

    So in conclusion, you load something with mode='0', you output it, and than to output the before last value of that you change to mode='1'. This works the same as a shift to right register which adds a '0' in its MSB after you have shifhted the register.

    - - - Updated - - -

    The before last value = next-to-last



    •   Alt11th January 2017, 16:32

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    Re: Analizing a VHDL program code

    Hi everyone, sorry i was very busy today and im finally back.
    It's not that i'm lazy or something but it's just that i'm not really into programming as much as my uni wants me to..I'm studying electronics engineering yet we have close to none practice with analog circuits(which i do love and spend an hour daily for improving my knowledge in it), we have lots of programming though..I don't seek any high grades, all i want to is pass the test because i have so many things in my mind right now, my brain is going to explode (lol)

    Going back to the topic:
    Yes, the "CKJ" was a typo, what i actually meant was "CLK".
    To ads-ee: actually, its me who chose the word "Program" for the architecture (ops). You see, english is not my main language, yet so the test isn't either. Our teacher has named it randomly (literally, he called it "random), so i just chose any word that would suit the syntax of HDL..
    Thank you all for your answers, i do really appreciate your help! Especially big thanks goes to CataM for giving me a good explanation. My friend has done some research with the code and found out that the code might be a parallel to serial converter, may that be right? It works kinda like shift to right register, am i right?



    •   Alt11th January 2017, 21:44

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    Re: Analizing a VHDL program code

    Quote Originally Posted by ads-ee View Post
    VHDL isn't programming it is actually digital logic design, but it seems you want to go into Analog design, so push back and don't take digital design classes, tell your uni you want to take only Analog/RF classes.

    ding, ding, ding! seems you have a friend that knows something about digital design, might want to talk to them next time you have a problem that needs a quick answer.
    Haha i guess i will talk to him about that lol.
    Talking about classes, i cant actually choose. They want us to learn logical devices..If i wanted to learn more about analog design i would have to choose a different uni but its too late since im a 4th year student already haha.



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    Re: Analizing a VHDL program code

    Quote Originally Posted by Janoy66 View Post
    It's not that i'm lazy or something but it's just that i'm not really into programming as much as my uni wants me to
    VHDL isn't programming it is actually digital logic design, but it seems you want to go into Analog design, so push back and don't take digital design classes, tell your uni you want to take only Analog/RF classes.

    Thank you all for your answers, i do really appreciate your help! Especially big thanks goes to CataM for giving me a good explanation. My friend has done some research with the code and found out that the code might be a parallel to serial converter, may that be right? It works kinda like shift to right register, am i right?
    ding, ding, ding! seems you have a friend that knows something about digital design, might want to talk to them next time you have a problem that needs a quick answer.

    - - - Updated - - -

    I still think CataM shouldn't have given that description, the whole point of a take home test IMO is to give you a problem that takes more time to solve than an in class test and requires that you perhaps have to do some research to solve it. As opposed to having someone else basically take parts of the test for you (answering the questions you cannot figure out), effectively cheating.

    https://www.csusm.edu/dos/studres/wwwc.html



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    Re: Analizing a VHDL program code

    Quote Originally Posted by Janoy66 View Post
    My friend has done some research with the code and found out that the code might be a parallel to serial converter, may that be right? It works kinda like shift to right register, am i right?
    I have explained how it works. Yes, it loads some parallel data with mode='0', stores it, and with mode='1' takes it out like a shift to right register adding '0' to its MSB.

    Quote Originally Posted by Janoy66 View Post
    Teacher gave as a test to do at home and i have struggles with one of the test.
    I agree with ads-ee. I did not read that at the very beginning. I thought it was a practicing problem.



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    Re: Analizing a VHDL program code

    Well, that was only one question, but it was worth 2 points. The other 4 test questions were more simple and i did them. We also had to write a code for an ASM machine, me and my colleague wrote the code together (by using an example) and it did work. I only slept 3,5hours because i was super busy and i literally didnt have enough time for this test..that is the main problem..



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    Re: Analizing a VHDL program code

    Quote Originally Posted by Janoy66 View Post
    Haha i guess i will talk to him about that lol.
    Talking about classes, i cant actually choose. They want us to learn logical devices..If i wanted to learn more about analog design i would have to choose a different uni but its too late since im a 4th year student already haha.
    just so you know, analog design these days is mostly digital. there is no harm in learning both.



    •   Alt12th January 2017, 20:18

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    Re: Analizing a VHDL program code

    Quote Originally Posted by Janoy66 View Post
    Well, that was only one question, but it was worth 2 points. The other 4 test questions were more simple and i did them.
    so if each question was worth 2 points: 5*2 = 10, therefore assuming you did all the other questions correctly getting this extra question results in a change of marks from 80% to 100%. You do realize that makes it unfair for those that actually spent time on working out the questions themselves. Those students may have gotten only 1 point on that question and ended up with a 90% mark, whereas you got the answer from a professional engineer that does this for a living (so is going to know the answer at a glance).

    That is why I don't answer homework or test questions, but instead try to get the student to figure the problem out or look at it in a different way.



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    Re: Analizing a VHDL program code

    Quote Originally Posted by ads-ee View Post
    so if each question was worth 2 points: 5*2 = 10, therefore assuming you did all the other questions correctly getting this extra question results in a change of marks from 80% to 100%. You do realize that makes it unfair for those that actually spent time on working out the questions themselves. Those students may have gotten only 1 point on that question and ended up with a 90% mark, whereas you got the answer from a professional engineer that does this for a living (so is going to know the answer at a glance).

    That is why I don't answer homework or test questions, but instead try to get the student to figure the problem out or look at it in a different way.
    Sorry i wasnt deep enough with my reply.
    The test question i showed you on there was worth 2points, we had 4 more questions: 0.5p,0.5p,0.5p and 1,5p. Our class group consists of ~15 students and we all work as a team so most of them had similar answers to each others.
    I actually dont really about the grade as long as i pass..Since its not something i enjoy doing (vhdl).If i ever teach (super rarely), i do it because i dont want to retake the test..I just started working a real job (professional job) this summer and realized that university hasnt taught me much, i am pretty strong at electronics (compared to my classmates), and its all because i spend my own free time learning it.



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    Re: Analizing a VHDL program code

    Quote Originally Posted by Janoy66 View Post
    The test question i showed you on there was worth 2points, we had 4 more questions: 0.5p,0.5p,0.5p and 1,5p.
    Oh, my then my math was wrong it's actually...
    0.5+0.5+0.5+1.5+2 = 5 pts so that one question was worth 2/5 or 40% of the grade, which I consider even more of an issue. Even if you get all the other problems correct that is only a 60% mark and that in the USA would be the lowest passing grade possible.

    Our class group consists of ~15 students and we all work as a team so most of them had similar answers to each others.
    I actually dont really about the grade as long as i pass..Since its not something i enjoy doing (vhdl).
    My only issue with such a statement is that getting a good/passing marks on something you actually don't know is basically a lie. I've interviewed enough liars in my time. Put them on the spot (they claim to be an expert in VHDL/Verilog) and it turns out they can't even code a counter correctly and had top marks in their class. Seems to me that their degree isn't worth what their marks claim, this is why I could care less what phenomenal marks a recent grad has, but instead interview with the intent to see if they can actually think and analyze a problem.

    I actually dont really about the grade as long as i pass..Since its not something i enjoy doing (vhdl).
    If you don't like it and aren't good at it, then IMO you should probably not have a passing grade (you probably should have dropped the class once you realized you didn't like it). I suppose wherever you are going to school doesn't allow you to specialize in a area you actually like and are good at, which I consider a disservice to the students and probably a push to cater to "donations" from industry for a certain type of engineer (like all engineers are supposed to be round pegs even when they are a square peg being force into that round hole )

    Sorry about getting on my soapbox, but I think the entire university system in many locations places too much emphasis on grades (marks) than on producing skilled engineers that can solve problems without having a solution book with a similar problem. I'm happy that you've at least taken the initiative to try to learn more than your colleagues by speeding your free time learning electronics.



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