+ Post New Thread
Results 1 to 3 of 3
  1. #1
    Junior Member level 3
    Points: 936, Level: 6

    Join Date
    Jan 2013
    Posts
    26
    Helped
    0 / 0
    Points
    936
    Level
    6

    How to extract power profile in Design compiler and SoC encounter

    Dear all,

    I need to feed a sample circuit with a number of random inputs (say for example 1000 input patterns) and then obtain a power trace (power consumed by the circuit during applying the input patterns). As the test circuit may not be small or the number of input patterns may be high, i don't want to use Hspice as it may take a long time. So I want to use Synopsys design compiler or SoC encounter tools to do this. I think such work is possible in both tools but i don't know how to do it. Please some help me. Thanks.

    •   Alt11th January 2017, 10:54

      advertising

        
       

  2. #2
    Advanced Member level 4
    Points: 5,016, Level: 16

    Join Date
    Apr 2016
    Posts
    1,058
    Helped
    188 / 188
    Points
    5,016
    Level
    16

    Re: How to extract power profile in Design compiler and SoC encounter

    do a simulation of the circuit using the inputs you want. then use encounter to do a power estimation. typically you would use a vcd file for this purpose.



    •   Alt11th January 2017, 22:08

      advertising

        
       

  3. #3
    Junior Member level 3
    Points: 936, Level: 6

    Join Date
    Jan 2013
    Posts
    26
    Helped
    0 / 0
    Points
    936
    Level
    6

    Re: How to extract power profile in Design compiler and SoC encounter

    Quote Originally Posted by ThisIsNotSam View Post
    do a simulation of the circuit using the inputs you want. then use encounter to do a power estimation. typically you would use a vcd file for this purpose.
    Thanks for your reply. I check it.



--[[ ]]--