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  1. #1
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    How to extract power profile in Design compiler and SoC encounter

    Dear all,

    I need to feed a sample circuit with a number of random inputs (say for example 1000 input patterns) and then obtain a power trace (power consumed by the circuit during applying the input patterns). As the test circuit may not be small or the number of input patterns may be high, i don't want to use Hspice as it may take a long time. So I want to use Synopsys design compiler or SoC encounter tools to do this. I think such work is possible in both tools but i don't know how to do it. Please some help me. Thanks.

    •   Alt11th January 2017, 10:54

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  2. #2
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    Re: How to extract power profile in Design compiler and SoC encounter

    do a simulation of the circuit using the inputs you want. then use encounter to do a power estimation. typically you would use a vcd file for this purpose.



    •   Alt11th January 2017, 22:08

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  3. #3
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    Re: How to extract power profile in Design compiler and SoC encounter

    Quote Originally Posted by ThisIsNotSam View Post
    do a simulation of the circuit using the inputs you want. then use encounter to do a power estimation. typically you would use a vcd file for this purpose.
    Thanks for your reply. I check it.



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