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    [VHDL NEXYS 3] new to this language, need help

    Hello guys,

    so i don't know this program very well ( i know little bit) and i need to write a program that is downcounting from 3B (HEX) to 0 with speed of 1 second, and it has to have Start/Stop and Reset on Nexys3. So basically 1 min downcounter...

    Can you give me some instructions or whole code i don't know

    •   Alt7th January 2017, 15:32

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    Re: [VHDL NEXYS 3] new to this language, need help

    Hi,

    Go step by step:
    * First connect the buttons. Follow standard circuits.
    * then connect a LED.
    * then implement a simple start/stop function. This should switch ON/OFF the LED. You will learn you need debouncing to make it work properly.
    * then implement a 1s event. It's just a divider from your system_ clock. Toggle the LED. It will toggle with 0.5Hz.
    * then implement a down_counter. Implement the "set to 59". Implement to stop counting at 0.

    Klaus



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    Re: [VHDL NEXYS 3] new to this language, need help

    I don't have nexys 3, i need to simulate it. So i need to have entity with start, stop, reset and led? And can i write it in only one vhdl module?



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    Re: [VHDL NEXYS 3] new to this language, need help

    Can you give me some instructions or whole code i don't know
    Ask google. There are numerous VHDL eg of down-counters floating around.

    I don't have nexys 3, i need to simulate it.
    For simu you don't need the board. Xilinx ISE or Vivado should suffice.
    Sharing my ideas and knowledge + learning from the experiences of others is what I am looking for.
    Spoon feeding is not my cup of coffee, so I am ready to show you the path, but it is you who has to walk through it!



    •   Alt9th January 2017, 09:35

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    Re: [VHDL NEXYS 3] new to this language, need help

    Quote Originally Posted by jacksparrow93 View Post
    I don't have nexys 3, i need to simulate it. So i need to have entity with start, stop, reset and led? And can i write it in only one vhdl module?
    Yes you can write this counter code in one module, but keep the stimulus for that code in a separate testbench file. Only use synthesizable VHDL for the counter code. You can use any and all supported (by the simulator) keywords for the testbench code. Just remember to instantiate your UUT (the counter code) in your testbench.


    1 members found this post helpful.

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    Re: [VHDL NEXYS 3] new to this language, need help

    Quote Originally Posted by dpaul View Post
    Ask google. There are numerous VHDL eg of down-counters floating around.


    For simu you don't need the board. Xilinx ISE or Vivado should suffice.
    I found couple of up/down counter codes but its for DEC, i can't find any eg for HEX



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    Re: [VHDL NEXYS 3] new to this language, need help

    Any counter that counts in binary will suffice as a HEX counter as a HEX digit is a 4-bit binary nibble of data. Just make sure you define your counter width to be a multiple of 4-bits.



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    Re: [VHDL NEXYS 3] new to this language, need help

    Quote Originally Posted by ads-ee View Post
    Just remember to instantiate your UUT (the counter code) in your testbench.
    Xilinx ISE does that for you.



    •   Alt10th January 2017, 23:36

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    Re: [VHDL NEXYS 3] new to this language, need help

    hey guysm i was busy so i coudn't respond.

    So, i was working od it!
    I have this
    Code:
    ------------------MAIN MODULE
    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;
    
    
    entity counter is
    port(
    	start_stop, reset, clk: in STD_LOGIC;
    	led: out STD_LOGIC_VECTOR (6 downto 0)
    );
    end counter;
    
    architecture Behavioral of counter is
    signal temp: std_logic_vector (7 downto 0);
    signal cp_o: std_logic;
    begin
    S1: entity work.FreqDivGen generic map (1000000) port map (cp, cp_o);
    
    process(cp_o, reset, start_stop)
    begin
    	if(reset = '1') then
    		temp <= "00111011";
    	elsif(cp_o'event and cp_o = '1') then
    			if(temp = '0') then
    				temp <= "00111011";
    			end if;	
    			if(start_stop = '1') then
    				temp <= temp - 1;
    				else
    					temp <= temp;
    			end if;
    	end if;	
    end process;		
    
    	with temp select
    		led<= "0000001" when "0000", --0 (abcdefg)
    				"1111001" when "0001", --1
    				"0010010" when "0010", --2
    				"0000110" when "0011", --3
    				"1001100" when "0100", --4
    				"0100100" when "0101", --5
    				"0100000" when "0110", --6
    				"0001111" when "0111", --7
    				"0000000" when "1000", --8
    				"0000100" when "1001", --9
    				"0001000" when "1010", --a
    				"1100000" when "1011", --b
    				"0110001" when "1100", --c
    				"1000010" when "1101", --d
    				"0110000" when "1110", --e
    				"0111000" when others; --f
    end Behavioral;
    -----------------------------------
    
    ---------------------FREQDIVGEN MODULE
    --------------------------------
    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;
    --------------------------------
    
    entity FreqDivGen is
    generic(nfCLK: natural := 100);
    port(
    	clk: in STD_LOGIC := '0';
    	clk_o: buffer STD_LOGIC := '0'
    );
    end FreqDivGen;
    
    architecture Behavioral of FreqDivGen is
    begin
    
    process(clk)
    variable temp: integer range 0 to nfCLK/2 := 0;
    begin
    		if (clk'event and clk='1') then
    			temp:=temp+1;
    			if (temp>=nfCLK/2) then
    				clk_o<=not clk_o;
    				temp:=0;
    			end if;
    		end if;
    		
    end process;
    end Behavioral;
    -----------------------------------
    So last thing i have to do is something called TIME MULTIPLEXER, how to do that?



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