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Purpose of diodes inside FAN630A flyback controller

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treez

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Hello,
Can you confirm the purpose of the two series diodes in the FB pin of the FAN6300A Flyback controller? Is it just to ensure that optocouplers which cannot pull the FB pin fully down to 0V still manage to stop the controller from PWM’ing the power FET.

The diodes are seen on the block diagram of page 3 of the FAN6300A datasheet….
https://www.fairchildsemi.com/datasheets/FA/FAN6300A.pdf
 

As far as I can tell, they are only to delay the threshold at which the soft start circuit cuts out. The data sheet doesn't explain how the FB pin controls the soft start or how the soft start works. They are internal to the silicon and I would guess they only play a role when the soft start circuit is in operation and not afterwards.

Brian.
 
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The same diodes + voltage divider level shift circuit can be found in many controller ICs with internal error amplifier. May be they just copied a design template. I don't see the purpose of asking "what's the purpose of".

Just take it as is. The specified characteristic is achieved with this circuit in place.
 
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Expect FB has substrate diodes in both devices.
 
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Thanks, yes i expect so, but with the LT3799, we can pretty accurately set the voltage on the pwm comparator with just a resistive divider on the CTRL pin.....but we cannot do it like that with the FAN6300A because of the extremely poor tolerance on the internal pullup resistor in the FB pin of the FAN6300A.
Also the diodes in the FB pin of the FAN6300A make it awkward to set the voltage on the pwm comparator with a simple resistor (or divider) on its FB pin.
 

treez said:
The reason i am asking is because the LT3799 doesnt have these diodes, and i just wonder if that makes it more susceptible to damage due to voltages on the FB pin ringing below ground?
Click to expand...

The diodes appear to be AFTER the soft start circuit so I doubt they would provide protection at a pin before that circuit. If the pin has protection it will be achieved through diodes intentionally added or incidental through the manufacturing process. In the FAN630A the Zfb parameter is the input impedance although earlier in the data sheet it refers to it as "5K equivalent resistance", I see no reference to it being a pull-up or pull-down. As long as you present enough drive current to it I don't see a problem. I would not advise using Zfb as a parameter in an external divider network anyway.

Brian.
 
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Thanks, speaking again of the FAN6300A flyback controller, the block diagram on page 3 shows a 18V zener diode clamping the gate output voltage to 18V. Page 12 actually describes it as an 18V zener.
If we supply the FAN6300A with 20V, then that would surely mean some pretty high current spikes going through that zener every time the FET is switched ON?

FAN6300A flyback SMPS controller
https://www.fairchildsemi.com/datasheets/FA/FAN6300A.pdf
 

Page 7, "Output Section" shows VOH is much less than that at VDD so I doubt it would reach 18V from an internal source.

Interestingly, using the figures in the data sheet, typical output voltage with 12V VDD is 7.5V (= 0.625 of VDD) and if you scale it up to find what VDD would make the Zener conduct you get the absolute maximum VDD figure for the device.

Brian.
 

thanks, i see your point....there does indeed appear to be a high overhead voltage...kind of a dropout voltage of about 4.5V perhaps. So yes, from that i suppose the 20V input supply voltage would only lead to say a 15.5V voltage at the zener. (or maybe 0.625 of 20V as you say)
I mean........thats a presumption, based on the datasheets details, but not definite. Theres still the outside chance that a 20V Vcc supply to the chip could result in high spikes of current going through the zener.
Its surprising that they say that Vcc can be up to 30V, because that surely would result in overly high spikes of current in the zener and would be surely very unwise?
 

Using the calculation VOH = (VDD * 0.625) which admittedly is the minimum figure quoted, setting VDD at 20V would give an output of 12.5V, still well below the Zener voltage. I'm not sure how the output driver stage works, all it states is totem pole Bi-CMOS but it doesn't specify where the top of the totem pole is fed from. It doesn't appear to produce the full VSS to VDD output swing you might expect.

Brian.
 

thanks, thats very pertinent, its making me wonder why they need an 18V zener there at all...i mean, with the dropout voltage, surely it would never get up to 18V?
 

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