What are the drawbacks of using a depletion type MOS?

I understand that the threshold for a N depletion type MOSFET will be negative. But, are there any drawbacks of using a depletion type MOS? Where are they used?

Depletion-mode MOSFETs are used when you want them to be on with zero gate to source voltage.
The big drawback is that they need an opposite polarity voltage from the drain-source voltage to turn them off.

Thus, for example, an N enhancement-mode MOSFET normally has a positive voltage on the drain and requires a positive voltage on the gate (both voltages with respect to the source) to turn it on. Therefore it needs only one supply voltage to operate as a switch.

In contrast, a depletion-mode device would need both a positive and negative supply voltage to operate as a switch.

They are handy for a few things.

One is beyond-the-rail operation, such as wanting an
on-chip LDO pass device that can be controlled from
within the product supply range, but drop voltage from
beyond (above). You could make a 2.5V supply from
5V, with a NMOS source follower, that has the gate
swinging between 0 and 2.5V.

Another, and similar, is use as a cascode "guard" that
does not need a bias to be generated - depletion FET
over enhancement FET will make the enhancement
("control") FET have a decent Vds, if the depletion
FET gate is grounded. I've done stuff like this on SOI
where I had 4 flavors apiece of NMOS and PMOS.
Also you see this in some "GaN FET" products like
IR's and TransPhorm's, a depletion mode GaN FET
over an enhancement mode low voltage MOSFET -
depletion FET stands off the voltage, enhancement
FET throttles the current.

Depletion mode FETs are often however "opportunistic"
and not as well controlled or as well behaved as the
"mainstream" regular FETs, if all are made within the
same process flow. There's your first-stringers and
your second-stringers, and depletion FETs are often
back-bench.

Depletion mosfets like the LND150 or IXCP10M45S get used as very simple high voltage current regulators.

In these high voltage applications the fact that the gate is normally on means no pull-up or other connection to the positive rail is necessary. Power flows and the circuit need only pull down the gate in order to regulate it. In high voltage applications this is a nice savings when a pull-up to 100V+ usually involves at least a couple decent sized resistors to handle the voltage/power.

Although they are 'normally on' their RDson is poor at 0V Vgs and a positive gate drive still reduces RDson significantly.

I would not say they are "drawbacks" but different operating behaviors. If one knows how to apply it, they can be quite useful.

Another useful application is as an active pullup.
If I remember correctly, that was the way NMOS logic worked. In the totem pole structure, the lower device was a regular enhancement Mosfet, whereas the upper device was a zero-bias depletion one.