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input clock precision loss after DCM

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bravoegg

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My system input clock is 9.14285Mhz. I connect it to an IO input pin, then passing it to a DCM generated by ipcore(Xilinx).

But the ipcore says the its clock output could only be as precise as 9.143Mhz.

What can I do to solve the discrepancy...

Thanks
 

What do you want the DCM to do?
Do you want the output frequency to be equal to the input frequency ?
 

The output is locked to the input the is no frequency drift. If the input was 33.333333333333333333333Mhz the DCM would report a clock output of 33.333MHz, but you will have an output that is the same frequency as the input clock. Rounding and significant bits are at play here.
 
yes, I want the output frequency to be equal to the input frequency. But the ipcore generator indicates there would be a slight difference between them. Input : 9.14285Mhz. Output: 9.143Mhz.
Is it inevitable?

- - - Updated - - -

Does this mean there's no difference between input and DCM output frequency? The displayed output frequency is just for show purpose?
Thanks.
 

Does this mean there's no difference between input and DCM output frequency? The displayed output frequency is just for show purpose?
Thanks.
The displayed output isn't just for "show purpose" - sometimes the DCM can't meet the requested frequency and it displays the nearest best.
However, in your case as ads-ee noted it's clearly a rounding issue. The DCM has no problem to output a 1:1 ratio clock from the 9.14285Mhz input.
 
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