coshy
Member level 3
I'd like to force some bunch of signals by derived multiple instances in verilog as below.
but that is not work with
Illegal operand for constant expression [4(IEEE)] error message.
So I'm looking for solution.
Code:
initial begin
for (bb=0; bb<3; bb=bb+1) begin
#10
for (ii=0; ii<19; ii=ii+1) begin
force sydnney.top.vx1.mpg.jpg[ii].trig.be[3] = bb;
...
end
end
end
but that is not work with
Illegal operand for constant expression [4(IEEE)] error message.
So I'm looking for solution.