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How do I use the force with array in verilog?

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coshy

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I'd like to force some bunch of signals by derived multiple instances in verilog as below.

Code:
initial begin
    for (bb=0; bb<3; bb=bb+1) begin                                                                        
     #10
     for (ii=0; ii<19; ii=ii+1) begin                                                                        
      force sydnney.top.vx1.mpg.jpg[ii].trig.be[3]                = bb;
      ...
     end
     end 
end

but that is not work with

Illegal operand for constant expression [4(IEEE)] error message.

So I'm looking for solution.
 

I have had many issues with force in the past, instead I used the command version supported by most simulators. It is more reliable.
 

I have had many issues with force in the past, instead I used the command version supported by most simulators. It is more reliable.
what are you talking about?
 

there is force, part of the verilog language
there is a command force, issued to the simulator

whenever I had issues with the former, I tried the latter.
 

Originally Posted by ThisIsNotSam View Post
I have had many issues with force in the past, instead I used the command version supported by most simulators. It is more reliable.
what are you talking about?

Have never used force in RTL but in simulation as ThisIsNotSam has already mentioned.

After you have compiled the design, in the simulator window, select the signal of your choice and right-click on it (you should see the force option) and then force it to the desired value. Then rerun your simu for # time, to see the effect of the force on your design.
Have used it, is direct, easy and clean!
 

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