cyrax747
Full Member level 3
Hi
I have synthesized a rtl using lvt and hvt cells.I dumped out netlist and when taking in to pnr tool ,i got errors saying the hvt cells are marked dont use.
so my physical data is not coming.i am unable to change the attribute also,again it is saying they are dont use cells.
remove attribute is also not working.how to fix this issue.
here is the error
1) Warning: The 'XOR2X1_HVT' cell in the 'saed32hvt_ss0p95vn40c' technology library does not
have corresponding physical cell description. (PSYN-024)
2) Compiling source file /home/training/my_pnr/counter_pnr/counter_syn.v
Warning: Cell 'DFFARX1_HVT.CEL' is created for undefined module 'DFFARX1_HVT'. (MWNL-294)
Warning: Cell 'INVX0_HVT.CEL' is created for undefined module 'INVX0_HVT'. (MWNL-294)
Warning: Cell 'NAND4X0_HVT.CEL' is created for undefined module 'NAND4X0_HVT'. (MWNL-294)
Warning: Cell 'NAND2X0_HVT.CEL' is created for undefined module 'NAND2X0_HVT'. (MWNL-294)
Warning: Cell 'OA21X1_HVT.CEL' is created for undefined module 'OA21X1_HVT'. (MWNL-294)
Warning: Cell 'NAND3X0_HVT.CEL' is created for undefined module 'NAND3X0_HVT'. (MWNL-294)
Warning: Cell 'OA221X1_HVT.CEL' is created for undefined module 'OA221X1_HVT'. (MWNL-294)
Warning: Cell 'AO22X1_HVT.CEL' is created for undefined module 'AO22X1_HVT'. (MWNL-294)
Warning: Cell 'HADDX1_HVT.CEL' is created for undefined module 'HADDX1_HVT'. (MWNL-294)
***** Pass 2 Complete *****
***** Verilog HDL translation completed! *****
------ Verilog Black Box Summary ------
9 black boxes found. Use -verbose option for detail information.
I have synthesized a rtl using lvt and hvt cells.I dumped out netlist and when taking in to pnr tool ,i got errors saying the hvt cells are marked dont use.
so my physical data is not coming.i am unable to change the attribute also,again it is saying they are dont use cells.
remove attribute is also not working.how to fix this issue.
here is the error
1) Warning: The 'XOR2X1_HVT' cell in the 'saed32hvt_ss0p95vn40c' technology library does not
have corresponding physical cell description. (PSYN-024)
2) Compiling source file /home/training/my_pnr/counter_pnr/counter_syn.v
Warning: Cell 'DFFARX1_HVT.CEL' is created for undefined module 'DFFARX1_HVT'. (MWNL-294)
Warning: Cell 'INVX0_HVT.CEL' is created for undefined module 'INVX0_HVT'. (MWNL-294)
Warning: Cell 'NAND4X0_HVT.CEL' is created for undefined module 'NAND4X0_HVT'. (MWNL-294)
Warning: Cell 'NAND2X0_HVT.CEL' is created for undefined module 'NAND2X0_HVT'. (MWNL-294)
Warning: Cell 'OA21X1_HVT.CEL' is created for undefined module 'OA21X1_HVT'. (MWNL-294)
Warning: Cell 'NAND3X0_HVT.CEL' is created for undefined module 'NAND3X0_HVT'. (MWNL-294)
Warning: Cell 'OA221X1_HVT.CEL' is created for undefined module 'OA221X1_HVT'. (MWNL-294)
Warning: Cell 'AO22X1_HVT.CEL' is created for undefined module 'AO22X1_HVT'. (MWNL-294)
Warning: Cell 'HADDX1_HVT.CEL' is created for undefined module 'HADDX1_HVT'. (MWNL-294)
***** Pass 2 Complete *****
***** Verilog HDL translation completed! *****
------ Verilog Black Box Summary ------
9 black boxes found. Use -verbose option for detail information.