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About the state of the FPGA I/O ports?

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FPGAs

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When the FPGA is just on power , having not been configured.
What is the I/O ports' state?
Hiz?
If the I/O port's voltage is as same as the power ,
it must have been burnt?,right?

And the FPGA's I/O port can simulate the "Swith"?
:)
 

This state is controlled by the M2 configuration pin (for spartan 2 fpga). You can set preconfiguration pull-up resistor, or you can leave the pins in high impedance state during configuration.

/pisoiu
 

It's in the flow state, that means the pins in high impedance state.
 

thank you for your replies.

but my fpga's pins are in the high level state when power on...
it must be burnt...
 

Hi,
Typically they are not trully HiZ. They have a week pullUp (to the VCCO of the Bank). So you see a HI if nothing is driving the line. (NOte this is done just to avoid bus chatter).

AMC
 

I'm using SpartantII300ELC Development Kit. Nomally, pins have no pull up resister. When I read a port which is without source, its value is low level. So I think, this depend on the kind of FGPA
 

Spartan-III have a pin called HSWAP_EN.

From the Xilinx doc:

A Low on this pin enables weak pull-up resistors on all pins that are not actively involved in the configuration process. A High value disables all pull-ups, allowing the non-configuration pins to float.

This is a dedicated pin, and is used for when the FPGA is not yet programmed.
 

Hi,

When FPGA/CPLD is unprogrammed or disable state I/O pins are in Hi-Z, weak Hi (pullup Hi) or Bus-keep state. In that states you can not burn I/O pin.

If chip is with good latchup protection and designed for live insertion, you can insert chip to socket with power on without worry.
 

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