Vias above mos gates

Is there any problem in placing a via above a MOS gates? I don't mean the contact between poly and metal 1, but a via between 2 metals.

Can this have impact on the matching in an array, even if the via is the same above every MOS in the array?

Not just the vias, it is often a good practice not to put lower metal layers over the gate for matching critical components (Vth matching gets worse). I'm sure you can find explanations for this on the internet, I'm not very confident about my processing knowledge so I wouldn't want to say something wrong.

Adding a via on the metal that passes above the gate requires insulation to be etched away and exposed to a second metal deposition. So I'm guessing via over gate would be worse than just metal over gate, but I don't have any information on this, it's just a guess. Good practice is avoiding lower level metals over poly altogether. But I don't think it really matters after some metal layer because there will be super thick insulation in between.

I only can find some info to avoid metal 1 above matched transistors, since i can have an impact on Vt. This makes perfect sense to me. There is no info I can find for other metal layers or vias, or just vias in particular.

But if there is no M1 there is also no via1. And if you have a via in a higher metal, the metal under the via (that is allowed) is blocking the via from the MOS.

I don't understand, do you have a follow up question or are you just confirming?

It was just confirming I already suspected, thank you.