UltraGreen
Junior Member level 3
Hello all ,
There are times, when I am not allowed to change the RTL, and all the clocking structure in the design are already optimized.
Still I face situations where I have negative slack ( setup as well as hold )
Some times by trying few strategies in Vivado, the tool solves the timing violations, but what if it doesn't ?
Question 1 : Can I always set false path for violation occurring at inter-clock-path ? ( provided , CDC is taken care in RTL )
Question 2 : How to solve Intra-clock-path timing violations ( setup and hold )
Thanks in advance..
There are times, when I am not allowed to change the RTL, and all the clocking structure in the design are already optimized.
Still I face situations where I have negative slack ( setup as well as hold )
Some times by trying few strategies in Vivado, the tool solves the timing violations, but what if it doesn't ?
Question 1 : Can I always set false path for violation occurring at inter-clock-path ? ( provided , CDC is taken care in RTL )
Question 2 : How to solve Intra-clock-path timing violations ( setup and hold )
Thanks in advance..