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Problem with design of a peak detector

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lolxiang

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Hi all

I was designing a peak detector with cadence. I used a very simple structure as shown in the first figure, an op amp drives a MOS diode to charge a hold cap, and feedback ensures the output tracks the input when input is higher.

The simulated waveform are as in p1 and p2 where some kind of oscillation is found. The op amp is unity-gain stable with that hold cap, but when I replaced the op amp with an ideal model the oscillation is gone. So I think it is due to the instability of the feedback, but with that diode I have no ideal how to tackle this problem. Any advice is appreciated.
 

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This indeed look a like stability issue for the opamp. With the probe in place, what is the phase margin and gain margin you obtain? Check with some initial condition on the capacitor, by inserting a voltage source in series with the capacitor.
 

The op amp is unity-gain stable with that hold cap
Click to expand...
But apparently not with RC in loop.

Need to tune the loop gain. Simple measure can be series R for hold cap. Unfortunately any solution for smoother track operation will probably worsen the hold performance, unless you can improve the OP GBW.
 

Most opamps have a maximum allowed capacitance that connects directly to its output. I agree that a resistor should be between the output of the opamp and the "rectifier diode".
The frequency is very low so why not use an ordinary silicon diode?

The first opamp does not have a negative supply so when the AC input signal swings negative then the input transistor on the opamp is destroyed. If a negative supply is added then another diode is needed to prevent the output of the opamp from saturating at its maximum negative output voltage.
 

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