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How to determine fpga resource usage per component and per process

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matrixofdynamism

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When we compile project in Altera Quartus ii, at the end we get resource usage. This gives total usage of logic elements, dsp slices and memory bits.

Is it possible to find how many fpga resources were used per component instance in design hierarchy and also per process?
 

When we compile project in Altera Quartus ii, at the end we get resource usage. This gives total usage of logic elements, dsp slices and memory bits.

Is it possible to find how many fpga resources were used per component instance in design hierarchy and also per process?

Quartus will break down resource usage to the entity level. Peruse the fitter report.

Kevin Jennings
 

Yes, there's a bit more than a single Flow Summary page in the compilation report. You also have a verbose resource utilization display in the Project Navigator's Hierarchy view.

also per process
No.
 

I hope I can use it to simplify the design if I can find some inefficiencies
 

I hope I can use it to simplify the design if I can find some inefficiencies

Looking at resource usage per entity isnt really going to tell you if something is written inefficiently. It just tells you if a specific block is a specific size. The synth has created a circuit for you that implements your code, so determining if something is "efficient" is more a design/architecture/code problem rather than something you'll determine from the fit report.
 

Looking at resource usage per entity isnt really going to tell you if something is written inefficiently. It just tells you if a specific block is a specific size. The synth has created a circuit for you that implements your code, so determining if something is "efficient" is more a design/architecture/code problem rather than something you'll determine from the fit report.
That's right of course. The resource utilization tells you at least which entities deserve primary attention when looking for saving potential.
 

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