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MIPS interoptive processor FPGA compatibility.....

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velu.plg

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FPGA info: virtex7 , xc7v200t . Is virtex7 FPGA Supports MIPS processor Soft IP. If it's supports the corresponding FPGA means what us the maximum achachievable frequency.And which MIPS series optimized for FPGA?
 

you know what a soft IP is, right? any FPGA can take it, as long as there are resources.
 

ThisIsNotSam said:
you know what a soft IP is, right? any FPGA can take it, as long as there are resources.
Click to expand...

The OP is still probably working on ASIC emulation and is trying to determine what clock frequency to run the emulated design at, but without doing any "work" to determine it on their own (they want to be spoon fed the information).

You do realize this is the same OP that was discussing the ARM A/R/M versions and which to use (in their ASIC emulation).

Seems like the tail wagging the dog if you ask me (ASIC emulation team telling the ASIC design team which processor they use for the ASIC so they can emulated the ASIC in an FPGA! Huh!?)
 

edaboard is a funny place. the things I have seen... cannot be unseen. 8-O
 

ThisIsNotSam said:
you know what a soft IP is, right? any FPGA can take it, as long as there are resources.
Click to expand...

Sure,but we can't achieve same clock frequency as such in ASIC. If you already tried this above scenario means tell me the maximum achievable clock frequency.
 

velu.plg said:
Sure,but we can't achieve same clock frequency as such in ASIC. If you already tried this above scenario means tell me the maximum achievable clock frequency.
Click to expand...

Sure, I will consult my favourite palm reader and let you know what the max freq is.
 

Don't want to stop anyone from doing other peoples homework. But as a first guess, the estimation from your ARM thread "well below 100 MHz" might fit.

It's quite obvious that the activities of professional IP core vendors to provide new soft cores almost vanished since the existence of powerful hard processor cores for recent FPGA families. The latest announcements are 4 or 5 years old.
 

velu.plg said:
not funny! I think you don't have experience in that domain. thanks for your response
Click to expand...

Even if I had actually implemented a MIPs processor in an FPGA, I would not tell you what the maximum acheivable frequency is, due to you expectations that edaboard members are your free resource to do your bidding and your work for you. Your posts almost always demand an answer and seem to imply that we must take care of your questions as you are an important person.

Get over yourself, and do your work.
 

To the OP, as things were/is still....

If you buy a soft-IP from a vendor, you have the right to ask your vendor what is the f(max) of the product you are buying. Target implementation can be ASIC or FPGA (the max clk will change accordingly).

If you are getting your core from any other source, you have to consult the docu that comes with that core (the max clk info may or may not there).

In the worst case just implement the core in your target FPGA and find it out yourself. It is not a great deal of work, you have the RTL, all you need to do is synth and timing analysis!
 

velu.plg said:
not funny! I think you don't have experience in that domain. thanks for your response
Click to expand...

On the other hand, YOU seem to have heaps of... wait, no. You don't. Let's recap what you just asked.

First you ask if an FPGA supports soft IP. << Evidence #1 that you are off base here.
Then you want to know the frequency of an IP that you didn't even bother to describe for a specific board that YOU might have. << Evidence #2. This is undergrad level of lost-in-design.
I am convinced you don't even know what MIPS is. << Evidence #3, I can even smell the years and years of industry experience here.
"Sure,but we can't achieve same clock frequency as such in ASIC". << Evidence #4, blanket statement that has nothing to do with the original query. Top notch.

Have you ever programmed an FPGA, ever? There is this magical thing called RTL that you can transform into circuits!
 

There are very different MIPS cores:
for example
**broken link removed**
and
**broken link removed**
The first is hundred times larger than the second.
---------

If you are interesting in MIPS implementation for educational purpose it is better to start from here:
**broken link removed**

The xc7v200t is the largest FPGA at the moment, and it is very inconvenient to work with it (I had the experience :). It is very expensive, consumes large current and so on.
And to prepare project suitable for the xc7v200t from scratch (port MIPS sources, for example) is not a job for one person in a reasonable schedule.

For educational purpose it is better to use small FPGA on cheap board. As far as I know mipsfpga is implemented on this board
https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&No=593
 
ThisIsNotSam said:
On the other hand, YOU seem to have heaps of... wait, no. You don't. Let's recap what you just asked.
---cut---
Have you ever programmed an FPGA, ever? There is this magical thing called RTL that you can transform into circuits!
Click to expand...

If you go back over the posting history of velu.plg you will see an initial severe misconception of what an FPGA even is. Then the progression through not understanding much about what you can put in them. Then there is a miraculous change to being very knowledgeable about FPGAs and system design (actually not) and telling very experienced people they don't know how to answer the questions posed, or telling others that they should answer their question because they want an answer.

- - - Updated - - -

_yes_ said:
The xc7v200t is the largest FPGA at the moment, and it is very inconvenient to work with it (I had the experience :). It is very expensive, consumes large current and so on.
Click to expand...

Uh, the largest part, is that so....
Virtex 7
Capture.PNG

Virtex UltraScale
Capture3.PNG

Virtex UltraScale+
Capture2.PNG

Well I'd say you are mistaken, it is, by far, not even close to being the largest part.
 

> not even close to being the largest part.

OK. The production line is moving. I've not use and forgot about the UltraScale families.
But in all cases: xc7v200t is complex multichip FPGA with some troubles in design partitioning and timing closure.
 

There's actually no xc7v200t, xc7v2000t is the largest Virtex 7 and - expensive enough - to be used only for very special applications like ASIC prototyping.
 

FvM said:
There's actually no xc7v200t, xc7v2000t is the largest Virtex 7 and - expensive enough - to be used only for very special applications like ASIC prototyping.
Click to expand...
I noticed that and was too lazy to point it out. :)

Yes, it pretty much is good for ASIC prototyping or massive SoC designs for military and research type projects. It also seems to be right in line with what the OP is doing, who still doesn't get the fact that any processor in an FPGA isn't going to run more than 100 Mhz unless it was designed from the ground up as an FPGA processor. Things like a Microblaze can run on a faster than 100 MHz clock.

Most ASIC emulations that I've been told about were run at more like 10-20 MHz (but that was 3-5 years ago) I'm sure with 28nm and below we can expect ASIC emulations to run at 30 MHz.
 

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