Engineer4ever
Member level 3
Replica Biasing Circuit of Maneatis Delay Cell
Hello,
I am designing a Maneatis Delay Cell along with its replica biasing cell. I have a few questions regarding the replica cell:
1) Is it necessary for the transistors in the replica cell to work in the same region of operation as their replicas in the delay cell? I mean, does one pmos transistor has to work in triode and the other in saturation?
2) I know that Vctrl=Vdd-Vsw. My question is, does Vsw mean the output swing of the Delay cell or the op-amp?
3) In the half-buffer replica, why is the gate of one transistor connected to Vctrl? In other schematics, the gate of this transistor is connected to its drain.
Thanks in advance,
Hello,
I am designing a Maneatis Delay Cell along with its replica biasing cell. I have a few questions regarding the replica cell:
1) Is it necessary for the transistors in the replica cell to work in the same region of operation as their replicas in the delay cell? I mean, does one pmos transistor has to work in triode and the other in saturation?
2) I know that Vctrl=Vdd-Vsw. My question is, does Vsw mean the output swing of the Delay cell or the op-amp?
3) In the half-buffer replica, why is the gate of one transistor connected to Vctrl? In other schematics, the gate of this transistor is connected to its drain.
Thanks in advance,
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