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JTAG buffer chip for Altera FPGAs

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sherif123

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For Altera FPGAs,
How can I use the buffer chips like SN74LVC541 between the JTAG cable and the FPGA jtag pins?
 

Something like this perhaps:
Code: 
TCK ---> A1==>Y1 ---> Slave_TCK
TMS ---> A2==>Y2 ---> Slave_TMS
TDO ---> A3==>Y3 ---> Slave_TDI
Slave_TDO ---> A4==>Y4 ---> TDI

Is the buffer being used to protect the FPGA from ESD or something?

FYI it will require running the JTAG slower than the maximum allowable frequency.

- - - Updated - - -

BTW, a lot of JTAG pods have the TDI as an output and the TDO as the input so you connect same name to same name on both the controller and slave. So you might have to modify the connections in the above table.
 

ad-se,
Yes I want to protect the FPGA from the ESD.
I already made a circuit like you recommended. I used the chip 74LVC541ADB. I could read the FPGA using auto-detect. But I could not program it. It shows me an error msg. I had to remove the buffer chip.
 

If you are using a fast JTAG cable (e.g. USB Blaster II at default 24 MHz), it might be propagation delay problem, as mentioned by ads-ee. More likely it's a trivial problem of expected signal idle levels. You should copy the TCK pull-down and TMS/TDI pull-ups to the buffer inputs.

There may be also a problem of ringing TCK causing double edges. Try 22 - 50 ohm series resistors at the buffer outputs. The JTAG cables have it, too.
 

Unfortunately I cannot add series resistors on the PCB.
TCK pull-down and TMS/TDI pull-ups are already on the buffer inputs.

But thanks anyway.
 

Unfortunately I cannot add series resistors on the PCB.
TCK pull-down and TMS/TDI pull-ups are already on the buffer inputs.
Click to expand...
O.K., so it's no p/u-p/d problem. The FPGA JTAG circuit is very fast and can easily recognize ringing TCK edges in a several 100 MHz range, resulting in occasional double clocking. The issue is strongly affected by JTAG circuit layout and TCK driver impedance. I would insert a chip resistor for test, to clarify the problem cause. A TCK parallel capacitor near the FPGA (e.g. 10 - 20 pF) might help, too.
 

OK I will try what I can and tell you what happened.
Thanks.
 

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