verilog converts real into an integer

i need to use a real for some calculation but when i use that real, the integer part of it is used:
this does 3/2=1.5 instead of 3.3/2=1.65
and for 3.7: 4/2=2 instead of 3.7/2=1.85

this is because 2 is an integer, and it will do an implicit cast of 3.3 to an integer before the divide.
2.0 on the other hand is a real.

a = a/ 2.0;

should give you correct result.

this does 3/2=1.5 instead of 3.3/2=1.65
and for 3.7: 4/2=2 instead of 3.7/2=1.85

Click to expand...

Is this happening with the value displayed or the value effectively stored at the variable ? In other words, assuming that you're using the $Display function, are you using the correct formatter ?

surprisingly i still get the same result

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i use

Without defining the fractional size of the number in the %f argument, seems like it is rouding the last decimal digit.

actually i get 1.500000 printed but i need 1.650000

It might help to show a small self-contained example.

Gives me
# 1.650000

If there is a problem with your simulator, you might try displaying with "%g" or no format at all.

Vivado's simulator gives the same result 1.65 regardless of whether or not you use a/2.0 or a/2. I didn't think that the integer 2 would cause it to do integer math.
Also the 3.7/2 gives a 1.850000 result.

I had already tried that before asking this question. Im using www.edaplayground.com

This code:

gives the following results:
Aldec Riviera Pro 2015.06
# KERNEL: 1.650000
# KERNEL: 1.850000
# KERNEL: 333333333333.333313
# KERNEL: Simulation has finished. There are no more test vectors to simulate.
exit
# VSIM: Simulation has finished.

Icarus Verilog 0.9.7
1.650000
1.850000
333333333333.333313

GPL Cver 2.12a
1.650000
1.850000
333333333333.333313
0 simulation events and 0 declarative immediate assigns processed.
7 behavioral statements executed (1 procedural suspends).
Times (in sec.): Translate 0.0, load/optimize 0.1, simulation 0.1.
End of GPLCVER_2.12a at Fri Nov 11 15:52:38 2016 (elapsed 0.0 seconds).

Veriwell 2.87 (note does not work on last number due to > 32-bit)
1.650000
1.850000
0 Errors, 0 Warnings, Compile time = 0.0, Load time = 0.0, Simulation time = 0.0

Normal exit
Thank you for using Veriwell

Didn't test VCS or Incisive as I know those will behave correctly as I've used both in the past.

gives the following results

Click to expand...

Saves my confidence in having understood Verilog automatic type conversion correctly. There's absolutely no reason to perform a conversion to integer in the assignments in post #1.

Either the original Verilog program is different or the simulator is not complying with Verilog LRM.

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Could it be lack of a real division operator with the particular tool?

The website that OP mentions allows sharing of projects by generating an URL for it
This way could be checked where exactly the error lies.

Thanks but I already saw my mistake, actually I that code was a part of a larger code and I just noticed I accidentally assigned 3.3 to a reg then assigned that reg to real, and that's where it got sliced