Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Matrix Array - Help needed fro project using verilog code

Status
Not open for further replies.
R

ramdin2006

Newbie level 5
Joined
Nov 2, 2016
Messages
9
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
90
How can we check if the element of a 2D array is equal to 0 in verilog ?
 

Code: 
if (my_array [0] [0] == 1'b0)
 
Is this possible placing the if statement inside the genvar and for look because I want to check each element of an array zero or not ? And then assign specific function for the values if its zero or non-zero element? Because when I tried the above syntax its throwing an error "A is not a constant" ? Thanks
 

ramdin2006 said:
Is this possible placing the if statement inside the genvar and for look because I want to check each element of an array zero or not ? And then assign specific function for the values if its zero or non-zero element? Because when I tried the above syntax its throwing an error "A is not a constant" ? Thanks
Click to expand...

genvar is a the declaration of a variable used in a generate statement....I presume you mean generate in this case.

Need the code you wrote to understand why you are getting "a is not constant" based on your other thread about doing matrix math on arrays I can only assume that you are still writing software instead of Verilog.
 
The code is as below ! 

Code Verilog - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68

module top;
 
   wire[17:0]A[1:3][1:3];    // the matrices
   wire[17:0]B[1:3][1:3];
   wire[17:0]C[1:3][1:3];
 
   wire[(9*18)-1:0] Abits;   // bit-decomposed versions of the above
   wire[(9*18)-1:0] Bbits;
   wire[(9*18)-1:0] Cbits;
 
   genvar i,j;
 
   // set A and B with initial values
   generate 
      for(i=0; i<3; i=i+1)
         for(j=0; j<3; j=j+1) begin
            assign A[i+1][j+1] = i*3 + j;
            assign B[i+1][j+1] = i*3 + j + 1;
         end
   endgenerate
 
   // decompose A and B, set C
   generate 
      for(i=1; i<=3; i=i+1)
         for(j=1; j<=3; j=j+1) begin
            assign Abits[(((i-1)*3 + (j-1)) * 18)+17 -:18] = A[i][j];
            assign Bbits[(((i-1)*3 + (j-1)) * 18)+17 -:18] = B[i][j];
            assign C[i][j] = Cbits[(((i-1)*3 + (j-1)) * 18)+17 -:18];
         end
   endgenerate
 
   initial
      #1 $display("%4d %4d %4d\n%4d %4d %4d\n%4d %4d %4d\n",
                  C[1][1], C[1][2],C[1][3],
                  C[2][1], C[2][2],C[2][3],
                  C[3][1], C[3][2],C[3][3]);
 
   mmult3x3 U1(Abits, Bbits, Cbits);
endmodule
 
module mmult3x3
   (input  wire[(9*18)-1:0] AI,
    input  wire[(9*18)-1:0] BI,
    output wire[(9*18)-1:0] CO);
 
   wire[17:0]A[1:3][1:3];
   wire[17:0]B[1:3][1:3];
   wire[17:0]C[1:3][1:3];
 
   genvar i,j;
 
   generate 
      for(i=1; i<=3; i=i+1)
         for(j=1; j<=3; j=j+1) begin
            assign A[i][j] = AI[(((i-1)*3 + (j-1)) * 18)+17 -:18];
            assign B[i][j] = BI[(((i-1)*3 + (j-1)) * 18)+17 -:18];
            assign CO[(((i-1)*3 + (j-1)) * 18)+17 -:18] = C[i][j];
         end
   endgenerate
 
   // this is the bit that matters - everything else just works around shortcomings 
   // in the language:
   generate 
      for(i=1; i<=3; i=i+1)
         for(j=1; j<=3; j=j+1)
            assign C[i][j] = A[i][1]*B[1][j] + A[i][2]*B[2][j] + A[i][3]*B[3][j];
   endgenerate
endmodule


I think this is the hardware approach. This code works fine.
This does matrix addition. But I want to check if the element inside the array is zero or non-zero and assign specific function for the values. Is this is possible ? Thanks.

- - - Updated - - -

Sorry above code does matrix multiplication !
 
Last edited by a moderator:

ramdin2006 said:
The code is as below !

I think this is the hardware approach. This code works fine.
Click to expand...

Simulation does not mean it's hardware, there are a lot of things you can do that don't work in synthesis. Your "hardware" (I use the term loosely) has no inputs or outputs so will be completely deleted by any synthesis tool.

Using wires to store matrix elements is not hardware you've just made a Verilog software program.
the reg type is used for storing values. these if written along with always @ (posedge clk) blocks where all the assignments are done infer Flip-flops or memory (if you code it according to the correct synthesis template).

What you have written will attempt to build a huge combinational circuit that will be very very very very slow. Without a clock and pipelined design techniques this design is worthless for use in any technology (even if it manages to synthesize).

You need to learn digital logic design first before writing Verilog. Can you draw a schematic using gates, Flip-flops, memories that does this matrix operation? Once you do that you write a Verilog hardware description of that circuit.


// this is the bit that matters - everything else just works around shortcomings
// in the language:
Click to expand...
The shortcomings aren't in the language the shortcoming is in your understanding that Verilog is a HARWARE DESCRIPTION LANGUAGE, you describe in excruciating detail the Flip-flops, the memories, the gates that make up a digital design. I suppose this is a good reason for teaching HDLs starting with structural code, it's more like hooking up ICs on a PCB than software coding. Trouble is once they introduce if statements students immediately start writing software Verilog/VHDL instead of keeping in mind they are still designing hardware.

- - - Updated - - -

FYI, the first VHDL design I wrote, I drew schematics for the entire design on paper before I started coding anything...

...and the design worked the first time it was download on the FPGA with absolutely NO simulation. Of course I was an EE board designer before I became an FPGA engineer and nearly all the boards I designed worked from their first time powered up.
 
Is it possible for you write the code? Will be helpful to know how the flow works with a sample program. Considering matrix addition. Please.
 

ramdin2006 said:
Is it possible for you write the code? Will be helpful to know how the flow works with a sample program. Considering matrix addition. Please.
Click to expand...

There is that word again...(head shaking)...

Synthesizable Verilog is not programming it is digital hardware design. Sure you can write Verilog programs, but those are usually referred to as TESTBENCHES.

And sorry, but no I won't write the code for you. I have better things to do in my spare time.

- - - Updated - - -

Here I'm feeling sorry for you...
Code Verilog - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

// multiply and add code that does the following:
// (a * b) + c
 
reg [31:0] mult_out, result;
reg [15:0] a, b, c;
 
always @(posedge clk) begin
 
  // pipeline stage 1, to multiply a * b
  mult_out <= a * b:
 
  // pipeline stage 2, to add the multiplied a * b result with c
  result <= mult_out + c;
 
end

Of course this leaves out all the stuff like top level ports, and how a, b, c are sourced and where the result goes. It also leaves out any kind of control, which would be done in an FSM and address generators to create the addresses used to index into the RAM that holds the matrix values.

I think this design is far outside your current level of expertise and knowledge and I think you should concentrate on learning the basics of digital design first.

Or stick with things like Zynq and just learn the simple stuff like loading RAM with data and use a C program running on the ARM to do the matrix operation heavy lifting.
 

This is a small multiply followed by a ternary add for timing, and 27 multiply + 9 ternary adds for area.

I don't like how every HW developer assume every design ever made will be run at the maximum frequency possible, and in a device with almost no area.

As an example, I worked on a contract 6 years ago. The design max frequency was somewhere in the Fmax/4 to Fmax/3 range for a Cyclone 3 or Cyclone 4. There was an aspect of the design that had a small control loop. I had coarsely tuned it earlier, and over a weekend I did a sim of a PID control. Just for the fun of it, I put the full PID line into the code -- multiple multipliers and a ternary add. The result wasn't even in the top 100 for slack -- easily met timing.

There are multiple points here:
1.) Once you get to the Fmax/3 range it becomes MUCH harder to reason about timing for complex logic. Most "complex" logic ends up having a lot of parallel branches resulting in fewer level of logic than first expected. Near Fmax, nothing works -- all logic must be small and simple. At that point it is easy to determine when something is too complex.
2.) You should know what to expect from your design. You should know you are making a HW design and have an estimate of the upper/lower bounds of area and performance. If you wrote that code and didn't realize it was a delay of a multiply + adder-tree or similar, you need to think more about HW.
3.) If you don't have a strong latency requirement, but do have a deadline, it is often better to add a pipeline stage or two. Just to be sure.
4.) VHDL/Verilog make pipelining deceptively easy. Use a good naming convention and have comments and a clear coding style for any pipeline. Make sure to know the difference between cycle-delay and sample-delay.
5.) There is a difference between "I had to do X" and "I did X and it didn't fail". In some cases it doesn't matter because "doing X" or not "doing X" had no significant difference in area/power, and ensured a high-perforce design with no last minute re-design issues.

--edit, I also like the extra effort to help people, ads-ee. I feel that the best developers have become to jaded to put even good faith effort into answering questions. This is just one of those cases where I've seen someone put a month of effort into over-complicating a design by solving a problem that never existed.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top