Help!! Questions on All types of resistances in Transistor model.

Hello folks,

Please help me out for solving this two confusions:

[1] Can anybody explain me in details about the on resistance, output resistance and load resistance in a transistor model?

[2] I am getting confused dealing with "resistance seen" from output node of a transistor. specially when some other resistors comes in parallel or in series with the load resistance.

These differences pertain to mode of operation mostly.
"On" resistance is resistance, desired to be low, from
drain to source in the hard-gate-driven linear region. Of
course a weakly driven FET has an on resistance too.
Just lousy.

"Output" resistance -is- "on" resistance, when the FET is
"on". But it's more of interest (i.e. different interest) in
analog applications or when the device is supposed to
be "off". Analog amplifier stage gain is gm*Ro (and I will
not diverge into explaining that here; read a book or
at least Wikipedia). Ro is the (parallel sum) output
impedance consisting of the gain element output
resistance (again, D-S), whatever applies the counter-
load (perhaps a FET, perhaps a resistor, perhaps an
incandescent light bulb, who knows?). Higher is better
for voltage gain (see eqn). Higher is had by longer
channel, lightly-doped drain structures, cascode
circuit topologies and so on.

Load resistance is not the transistor's attribute, it's
the external element that pulls against the transistor
(without it, drain just sits on the floor muttering to
itself). Uselessly. A hammer without a nail, and no
walnuts to be found.

A minimum load resistance (and maximum
voltage) might be asserted for a particular device
for thermal or reliability reasons. But the transistor
(unless the load is a transistor also, set up right)
has no load resistance per se of its own.

"Resistance seen" pertains to the node. dV/dI. The
parallel network impedance (ground referred generally,
but current sources by definition don't much care
where you refer them). For example, if you have a
FET with an output characteristic as-biased where
@ Vds=2V, Id=2uA and @ Vds=2.1V, Id=2.1uA, the
FET Ro = (2.1V-2V)/(2.1u-2u) = 100Mohms. This is the
FET in question's "output resistance" -for that OP-.

Now suppose the "load" is another device, a PMOS
device which as-biased has @ Vds=-1.3V ID=-2uA
and @VDS=-1.2V ID=-1.8uA. This FET's Ro is
(-1.2V - -1.3V)/(-1.8u - -2u) = 500Kohms.

Now you may think your amplifier design is moving along
nicely because you've got a 100Mohm NMOS Ro and
gm*Ro (in isolation) is pretty sweet as a result. But
attach the load and the parallel sum ("looking in" as
you might say) is 100M || 500K, = (100M*500K)/(100M+500K)
= 498K and all of a sudden your gain went in the tank
to the tune of 1/200. Sweet.

@dick_freebird Thanks for the nice and detailed explanation. Is the PMOS load you saying about, is that one which "sits" above the main transistor? ( just in a OTA, pmos current mirror above the differential pair). So the counter-load (PMOS) resistance is that load resistance you explained? or this is the resitance which arrives from next stage PMOS transistor? Hope I can make yo understand about the doubt.

The next stage PMOS (if gate connected) would add no
conductance (load). It would depend on the next stage
(or stage-stage) topology. The example I gave would be
for something like an NMOS common-source gain stage
with a PMOS current-source load. In a useful case you
would add the next stage's loading impedance (if not
nil, like a gate terminal) to the parallel calculation. And
for AC, the reactive impedances as functions of frequency
as well.