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how to fix setup and hold on same path

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mepriyasingh

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Hi,
how to fix setup and hold on same path, if we fix hold increase setup violation, and if we fix setup increase hold violation.
 

do a setup fix with a margin. say, add 10-50 ps more of slack than the minimum. then fix hold.

this is simplistic, of course, but it works for small issues.
 
seem that your path has same clock latency path and applied OCV.
Please check if you remove the OCV effect on common logic of clock using CRPR or not.
 

seem that your path has same clock latency path and applied OCV.
Please check if you remove the OCV effect on common logic of clock using CRPR or not.

Common Path Pessimism Removal (CPPR) might make sense, but I think OP is asking a more simple question.
 

Common Path Pessimism Removal (CPPR) might make sense, but I think OP is asking a more simple question.

yes its looks basic question. Is it possible to have both setup and hold violation on a reg2reg path. if yes how to fix?
 

It is possible to have both setup/hold violations on the same reg2reg path: if you have big "delta delay", which is due to big coupling capacitance on some nets in the path. During setup analysis, the tool add this "delta delay" to the total path length (so you may have setup violations). During hold analysis the tool sustract "delta delay" from the total path length.

Try to minimize the coupling capacitance (increase wire spacing or change the metal layer).
 

It is possible to have both setup/hold violations on the same reg2reg path: if you have big "delta delay", which is due to big coupling capacitance on some nets in the path. During setup analysis, the tool add this "delta delay" to the total path length (so you may have setup violations). During hold analysis the tool sustract "delta delay" from the total path length.

Try to minimize the coupling capacitance (increase wire spacing or change the metal layer).

Thanks oratie,

Like if we do not consider crosstalk, is it possible. @90nm.
as i understand only either setup or hold will violate.

Thanks
 

example: I have a reg2reg hold is violated by -50ps in ff corner and the same path has the setup margin of +100ps in ss corner. (with any consideration of crosstalk analysis)
How to fix this?
 

example: I have a reg2reg hold is violated by -50ps in ff corner and the same path has the setup margin of +100ps in ss corner. (with any consideration of crosstalk analysis)
How to fix this?

by using delay cells.
 

sure to fix hold violation we add delay cell. but looking for some numbers.
and some more explanatory abt setup also.

example: I have a reg2reg hold is violated by -50ps in ff corner and the same path has the setup margin of +100ps in ss corner also suppose clock period of 1ns (with any consideration of crosstalk analysis)
 

sure to fix hold violation we add delay cell. but looking for some numbers.
and some more explanatory abt setup also.

example: I have a reg2reg hold is violated by -50ps in ff corner and the same path has the setup margin of +100ps in ss corner also suppose clock period of 1ns (with any consideration of crosstalk analysis)

you add enough delays cells until the -50ps turns into zero, and make sure what once was +100 doesn't turn negative. give or take some margin. that's the essence of it, and it's all automated by the tools.
 
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