QSYS - 2 masters , 1 slave

Hello,

I have an FPGA fabric DDR3 controller (UNIPHY) implemented in QSYS.
The Avalon MM interface of the DDR3 has 2 masters connected to it:

1. ARM HPS.
2. A custom logic block I designed myself.

I know, that in such case QSYS generates a Round Robin Arbiter behind the scene (invisible in QSYS).

My question:

Suppose the HPS issues a read request and the DDR3 controller fetches the data back after n clocks.
Will the QSYS interconnect know that this data is intended only for the HPS (that sent this request in the first place) - or will it also strobe the Avalon MM "read data valid" signal that's connected to the custom logic block ?

In other words,
When master A issue a read request and the slave answers - will master B see the answer ?

From what I recall of the Avalon interface and looking back at the specification, a master is "locked" to a slave until the transfer is complete and the ordering of the data returned on a read (burst read) is in the order requested. From what is mentioned in the specification, which doesn't explicitly say so, a master should only see activity that is for it's specific requests. So in your case I would think slave responses to master A won't be seen by master B.

If you try running a simulation you should have your answer.