ASIC design flow procedure

I have just worked with tools like synopsys, Encounter for very simple designs. Can someone pls guide me with the design flow

ASIC design flow is

1) Write the verilog/vhdl code
2) simulate and verify the behavior of the design
3) Next we load the .v file in Synopsys and synthesize from RTL to get gate level implementation
4) We set the constraints according to the design requirement and also according to the technology specifications for ( area, nets width, net spacing, power, timing) and i suppose this comprises the SDC file.
(Also based on the constraints set the synopsys tool will synthesize/optimize the design accordingly, am i right?)
5) In synopsys after including the .v file, target and link libraries we can obtain the synthesized design which we can save as a gate level netlist file (ie .v file)
6) We simulate this gate level netlist file
7) Next In Encounter we import the netlist file and the SDC file from synopsys and we do floor planning, placement and all the physical design steps.


Please let me know if i am correct so far or if i have missed any steps. My question is i read for each step of physical design we save a file so as to verify after each step say placement, after routing the logic is still working fine. Which file is this? Kindly help!

2.5) For huge SoC designs there is something called HAL checks. I know that VCS and Cadence, HAL can be enabled during RTL compilation.
5.5) Depending on how much RTL modifications were done after the synthesis-engineer had proceeded with synth. the design, LEC can come in here.
6) This is not always necessary. Post layout simulation would be nice to do.

You are missing the DFT flow.
Google search can give you some nice flow steps. But important is which flow is followed at your work-place.
You can always ask your senior colleagues at your work-place to give you the flow. Every company has one!

dpaul, I have some comments.

interesting that you mentioned HAL, I used to teach that! And it is barely acknowledged. IMO it has nothing to do with SoC size. It is related to how paranoid a company is about their coding style.

About LEC, I would say it is very frequently done. When you factor in all the pipelining and retiming changes and new constraints, it is easy to miss something.

I could argue that 6 is very necessary but rarely feasible for even medium-sized designs.

Verification and test are separate from the implementation flow, and they can be as complex as. Some really tricky verification "closure" methodologies out there.

About the steps, your 3,4,5,6 steps would be existed in 1 step: synthesis.

About your question, to check the logic operation of post-layout design, we can have 2 kinds of verification:
1. Back-Annotation Simulation, using VCS, ModelSim....with inputs:
1.1 Verilog Nestlist + Parasitics delay info (usually SDF).
1.2 Both of them are extracted from post-layout database. ( or any step in Place&Route state that you wish )

2. Logic equivalence check, using Formality, Conformal ... with inputs:
2.1 Reference netlist ( ussually the one Synthesis with DFT circuit inserted )
2.2 Implemenation netlist ( from Place&Route database )

There 2 verifications should be performed for 1 design. You can not use one to confirm the other.