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How can I find the no load wire in synthesis?

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coshy

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Hi.

When I synthesis with design compiler as below code, I found the wire 'data' is removed but no reported.

Is there any possible way to know DC has been removing that wire data?

Code Verilog - [expand]
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module test (
input clk,
input a,
input b,
output c
);
 
reg c;
wire data;
 
always @(posedge clk)
begin
   c <= a+b;
end
endmodule
 
Last edited by a moderator:

Recheck your synth report.
Search the report with "data".
 

There is no any data
 

What is "no any data"?
Have you checked carefully?
Have not worked with DC for a long time. In many there cases a short log file is generated and a detailed report file is generated. If you don't find the info in the log file, look in to the report file.
 

dpaul said:
What is "no any data"?
Have you checked carefully?
Have not worked with DC for a long time. In many there cases a short log file is generated and a detailed report file is generated. If you don't find the info in the log file, look in to the report file.
Click to expand...

I have double checked but there is no any word about 'data'.
Is there any special command to see that ?
 

OP,

please be more clear about what exactly you are looking for. I am very confused.
 

ThisIsNotSam said:
OP,

please be more clear about what exactly you are looking for. I am very confused.
Click to expand...

Don't you see that I declared wire data in the code, it doesn't show as any log after synthesis.
 

I am sure if a reg or wire is not used but remains at the RTL level, then it is removed by the synth tool later. And the synth tool does report that the particular reg/wire has been removed.

Now I don't know how to give a better response to the OP's question.

Even the design is very small, not a million gate ASIC.

One minute. cosy............
Did you manage to go past simulation. Can you compile your code? Because your RTL is wrong! What are the port sizes?
 
Last edited:

coshy said:
Don't you see that I declared wire data in the code, it doesn't show as any log after synthesis.
Click to expand...

oh, that is so simple. if you had checked the log, you would see that data was removed because it doesn't drive anything.

but by the way you described the problem, it seems like you are talking about wireload models.
 

oh, that is so simple. if you had checked the log, you would see that data was removed because it doesn't drive anything.
Click to expand...
But OP says he has double checked the log and couldn't find any entry related to its removal. That is his problem!
 

Interestingly enough, I tried this in Xilinx Vivado synthesis (as I don't have any ASIC tools available) and the only warning reported is:
WARNING: [Synth 8-2611] redeclaration of ansi port c is not allowed [F:/test/test.v:8]
which is due to not declaring the reg in the same line as the ANSI output port...
output reg c

The wire data isn't even mentioned anywhere in the reports and I mean all of the reports/logs/transcripts/etc. The schematic view for both the elaborated HDL and the synthesized netlist doesn't even show the wire as having existed in the first place.
 

dpaul said:
But OP says he has double checked the log and couldn't find any entry related to its removal. That is his problem!
Click to expand...

most tools have different verbose modes, maybe that needs to be modified. I know that is definitely true for RTL compiler and genus.
 

Might be, Is there any option for solving such as this case?
 

Which command did you use to read/parse the Verilog file into DC run ?

Please try:

analyze -rtl <file.v> > analyze.log // or maybe analyze -verilog <file.v>
then
elaborate <top_design> > elaborate.log

After that, check one more time to see any Warning, Info or Error in analyze.log, elaborate.log ?

If there is none of them, that is Tool behavior to keep silient as default,
and there is no issue with your design if you dont need "data".
 

ThisIsNotSam said:
most tools have different verbose modes, maybe that needs to be modified. I know that is definitely true for RTL compiler and genus.
Click to expand...

This might be a likely reason!

-----------------------------------------

As for a non-ASIC tool such as Vivado synthesis, I have the excerpt from my current synth report ..\synth_1\runme.log

WARNING: [Synth 8-3332] Sequential element (\temac0_ctrl_inst/addr_reg[16] ) is unused and will be removed from module dual_temac_top__xdcDup__1.
WARNING: [Synth 8-3332] Sequential element (\temac0_ctrl_inst/addr_reg[15] ) is unused and will be removed from module dual_temac_top__xdcDup__1
.
.
.
 

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