matrixofdynamism
Advanced Member level 2
So I have tested the individual blocks with their testbenches and have to connect them together to create the actual design block. Basically it is a flash-ADC DMA. It receives signal from another part of design designating which "file number" to read from flash memory, it calculates address for the "metadata" of the "file" which it reads from the flash, this record explains the start and end address of this "file" (along with some other useful information) inside the flash which is then read continuously and sent to an ADC which is running at different clock rate via a clock crossing FIFO. This is the gist of it.
There are a lot of blocks at the same level of hierarchy that need to be connected together along with a few mux and demux. It is proving somewhat intimidating since many signals have rather long names of 3 - 4 words seperated by underscores and there are multiple instances of mux and demux in the design.
Could you highlight some approach I should take to make it easier to instantiate and port map the components? At this time it is looking rather complicated. Any recommendation on how to name signals is appreciated. Or is it that people would just ditch the HDL entry for schematic entry for this type of scenario?
There are a lot of blocks at the same level of hierarchy that need to be connected together along with a few mux and demux. It is proving somewhat intimidating since many signals have rather long names of 3 - 4 words seperated by underscores and there are multiple instances of mux and demux in the design.
Could you highlight some approach I should take to make it easier to instantiate and port map the components? At this time it is looking rather complicated. Any recommendation on how to name signals is appreciated. Or is it that people would just ditch the HDL entry for schematic entry for this type of scenario?