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SPI interface Vivado/SDK

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beginner_EDA

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Hi,
I would like to know how to implement SPI interface to work with microblaze having environment Vivado/SDK?
 

Either create your own AXI4-lite SPI or use the one in the IP library of the bd tool.
 
Hi,
I have added SPI interface to my existing Project having UART interface (see screenshot in red marks) but I am not sure about:
1. where I am suppose to connect another 2 unconnected pins(STARTUP_IO and ip2intc_irpt).
2. following critical warning during bitsream generation:
[Netlist 29-160] Cannot set property 'BOARD_PIN', because the property does not exist for objects of type 'pin'. ["c:/FPGA/Three_Channels/xapp1199/xapp1199_v1_2/kc705_smpte2022_56_rx/VoIP_RX_10G/VoIP_RX_10G.srcs/sources_1/bd/system_basic/ip/system_basic_axi_quad_spi_0_0/system_basic_axi_quad_spi_0_0_board.xdc":3]

and pointing to generated xdc files:
set_property BOARD_PIN {SPI_IO0_T} [get_ports io0_t]
set_property BOARD_PIN {SPI_IO1_T} [get_ports io1_t]
set_property BOARD_PIN {SPI_SS_T} [get_ports ss_t]

But there are no such pin available with the user guide of kc705 fpga board. That means do I need to map some GPIO pin and make some physical connection by self?

3. which port should I instantiate for spi part in top level design as pin is not clear to me.

4. After exporting hardware in SDK, where should I control spi part also not clear.

Any idea?
 

Attachments

  • spi.jpg
    spi.jpg
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Hi,
I have added SPI interface to my existing Project having UART interface (see screenshot in red marks) but I am not sure about:
1. where I am suppose to connect another 2 unconnected pins(STARTUP_IO and ip2intc_irpt).
Have you read PG153, specifically pages 19 & 22? The signals are describe for both of these.

2. following critical warning during bitsream generation:
[Netlist 29-160] Cannot set property 'BOARD_PIN', because the property does not exist for objects of type 'pin'. ["c:/FPGA/Three_Channels/xapp1199/xapp1199_v1_2/kc705_smpte2022_56_rx/VoIP_RX_10G/VoIP_RX_10G.srcs/sources_1/bd/system_basic/ip/system_basic_axi_quad_spi_0_0/system_basic_axi_quad_spi_0_0_board.xdc":3]

and pointing to generated xdc files:
set_property BOARD_PIN {SPI_IO0_T} [get_ports io0_t]
set_property BOARD_PIN {SPI_IO1_T} [get_ports io1_t]
set_property BOARD_PIN {SPI_SS_T} [get_ports ss_t]

But there are no such pin available with the user guide of kc705 fpga board. That means do I need to map some GPIO pin and make some physical connection by self?
don't know about this, I would have to attempt to implement this design, which I don't have time to do. Though each of these signals are likely the tri-state controls for their corresponding pins of the _o pin. I other words you are probably supposed to be instantiating tri-state (OBUFT) primitives for these outputs and these signals drive the tri-state control.

3. which port should I instantiate for spi part in top level design as pin is not clear to me.
The one called spi_flash is the spi interface. I'm not sure why you have this question. Maybe you don't know that this IP can be used for controlling the SPI configuration flash or as a standard 4-wire SPI master. Perhaps you are not configuring the right version?

4. After exporting hardware in SDK, where should I control spi part also not clear.
It's controlled via the AXI4-Lite interface and the base address can be found in the Address Editor tab.
 
The one called spi_flash is the spi interface. I'm not sure why you have this question. Maybe you don't know that this IP can be used for controlling the SPI configuration flash or as a standard 4-wire SPI master. Perhaps you are not configuring the right version?
Hi, I am looking for 4 wires(CLK, MISO, SIMO, SS) SPI to read the output and give the command to system(microblaze) from outside like UART Terminal and surely not SPI configuration flash.
But there is only one IP which is available in vivado. Does it mean I am not using the right one?
 

Your question and problem is not clear to me, but I'll try to answer from the bits & pieces I have understood.

1. where I am suppose to connect another 2 unconnected pins(STARTUP_IO and ip2intc_irpt).
Study the SPI IP spec carefully, it would be written there how these pins can be connected (don't have time to read the spec and extract that info for you).

But there are no such pin available with the user guide of kc705 fpga board. That means do I need to map some GPIO pin and make some physical connection by self?
On top of what ads-ee has said, I would like to add that the *_t signals looks like tri-state buffer control signals and they cannot be connected directly to an FPGA i/o port. Use an OBUFT as ads-ee has mentioned.

You have used a quad SPI and in the bd shown by you, only SPI_0 set has been used. Make sure you are making the proper connections.

But there is only one IP which is available in vivado. Does it mean I am not using the right one?
I think you are using the correct IP.

Bigger question is why are you using the SIP IP and what do you want to do with it?
If your connections are ok (you pass the Vivado bd rule check) then the uB can drive axi transactions that would write the control words in the SPI registers which would in turn drive the o/p SPI signals.
 
Last edited:

Bigger question is why are you using the SIP IP and what do you want to do with it?
Hi,
I have UART Terminal for my project to control the program like setting IP address, UDP port etc from terminal and also to see the output (printf function) of the program on the terminal.
Now I would like to replace this task of UART with SPI.

and it's not clear to me how to proceed?
 

Referring to the block diagram....

You need to remove the axi_uartlite_1 from the M00_AXI (AXI Interconnect module) and replace it with your SPI module. Take the help of Vivado bd flow tool for interconnections.
 

Hi,
I tried adding spi as separate(keeping UART as above diagram) component and also completely replacing UART with SPI as you mentioned.
but the question is what is the steps after that:
1. There is no pins of SPI in kintex kc705, how I can instantiate to top level module and specially how I can connect to outside world like via SPI cable or something like that?
2. After exporting hardware to SDK, the base address available in Address Editor tab but don't know in which function should I use this address.
For UART this is the part of C program which controlling it:
Code:
/**
 * Fetch input from UART then callback voip_contrl_app to
 * process the selection
 */


#include "xuartlite_l.h"

void get_voip_ctrl_app_input(void)
{
	if (!XUartLite_IsReceiveEmpty(STDIN_BASEADDRESS)){
		inchar = (u8)XUartLite_ReadReg(STDIN_BASEADDRESS, XUL_RX_FIFO_OFFSET);
		xil_printf("%c\n\r",inchar);
		voip_ctrl_app(inchar);
		voip_ctrl_app(CARRIAGE_RETURN);
	}
}
but what should I do for SPI?
 
Last edited:

1. There is no pins of SPI in kintex kc705, how I can instantiate to top level module and specially how I can connect to outside world like via SPI cable or something like that?
Have you read the chapter "Testing the Example Design on a KC705 Board" in the pg153-axi-quad-spi.pdf document? There seems to be some info there!
Basically you can to connect the SPI ports to the kc705 ports as standard i/p or o/p ports. So you can use any set of GPIO ports available on the Kintex (I don't use Kintex, so can't pin point you to the pins right now).

2. After exporting hardware to SDK, the base address available in Address Editor tab but don't know in which function should I use this address.
Keep it simple. Just read-from/write-to valid AXI addresses.

Below is a simple eg. of writing to an AXI address.
Code:
#include <stdio.h>
#include "platform.h"

#define LOC3 (*(unsigned int *)0xf0000000) // This is the axi address 

int main()
{
    init_platform();

    LOC3 = 0xcafeface; // Write data "cafeface" to LOC3

    cleanup_platform();
    return 0;
}

- - - Updated - - -

Correction: Basically you can connect the SPI i/p or o/p ports to the kc705 pins. So you can use any un-used set of GPIO pins available on the Kintex (I don't use Kintex, so can't pin point you to the pins right now).
 
Basically you can to connect the SPI ports to the kc705 ports as standard i/p or o/p ports. So you can use any set of GPIO ports available on the Kintex
This is the xdc file generated after adding spi ip :

set_property BOARD_PIN {SPI_IO0_T} [get_ports io0_t]
set_property BOARD_PIN {SPI_IO1_T} [get_ports io1_t]
set_property BOARD_PIN {SPI_SS_T} [get_ports ss_t]

So, if I replace this part in xdc file with this:

set_property PACKAGE_PIN AB25 [get_ports XADC_GPIO_0]
set_property IOSTANDARD LVCMOS25 [get_ports XADC_GPIO_0]
set_property PACKAGE_PIN AA25 [get_ports XADC_GPIO_1]
set_property IOSTANDARD LVCMOS25 [get_ports XADC_GPIO_1]
set_property PACKAGE_PIN AB28 [get_ports XADC_GPIO_2]
set_property IOSTANDARD LVCMOS25 [get_ports XADC_GPIO_2]

and maps:
io0_t ->XADC_GPIO_0
io1_t -> XADC_GPIO_1
ss_t -> XADC_GPIO_2

then it should work?

C programming part i am working on and will let you know.
 

It was already pointed to you in #4.

Look at pg153-axi-quad-spi.pdf, Pg. 5, Figure 1.1.
You have the set of signals, io0_o (o/p signal), io0_i (input signal), io0_t(control signal). These are also valid for SCK and SS. You *cannot* connect these directly to FPGA IO pins. You have to put a tri-state buffer in between.
{ io0_o, io0_i, io0_t} <--> 3 state buffer <--> FPAG pins
That means for each of the SPI ports you will have individual 3-state buffers to enable them to be connected to the o/p.

How to use a 3 state buffer: Read this - http://forums.xilinx.com/t5/Synthesis/Use-of-Tristate-Buffers/td-p/105365
You can either use behavioral RTL description or directly instantiate the Xilinx primitive OBUFT (3-state output buffer).

Download the doc ug471_7Series_SelectIO.pdf, search for OBUFT and read how it behaves.

Hope this is now clear.
 
Last edited:
You can either use behavioral RTL description or directly instantiate the Xilinx primitive OBUFT (3-state output buffer).
Download the doc ug471_7Series_SelectIO.pdf, search for OBUFT and read how it behaves.
Hi,
Thanks for pointing OBUFT. I am complete newbie to this iobuff stuffs. so sorry if my question is so silly. In ug471 you mentioned for OBUFT, it is as in attachment. and its generated IP(in synthesis) has port:
Code:
ENTITY system_basic_axi_quad_spi_0_0 IS
  PORT (
    ext_spi_clk : IN STD_LOGIC;
    s_axi_aclk : IN STD_LOGIC;
    s_axi_aresetn : IN STD_LOGIC;
    s_axi_awaddr : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
    s_axi_awvalid : IN STD_LOGIC;
    s_axi_awready : OUT STD_LOGIC;
    s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
    s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
    s_axi_wvalid : IN STD_LOGIC;
    s_axi_wready : OUT STD_LOGIC;
    s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
    s_axi_bvalid : OUT STD_LOGIC;
    s_axi_bready : IN STD_LOGIC;
    s_axi_araddr : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
    s_axi_arvalid : IN STD_LOGIC;
    s_axi_arready : OUT STD_LOGIC;
    s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
    s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
    s_axi_rvalid : OUT STD_LOGIC;
    s_axi_rready : IN STD_LOGIC;
    io0_i : IN STD_LOGIC;
    io0_o : OUT STD_LOGIC;
    io0_t : OUT STD_LOGIC;
    io1_i : IN STD_LOGIC;
    io1_o : OUT STD_LOGIC;
    io1_t : OUT STD_LOGIC;
    ss_i : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    ss_o : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
    ss_t : OUT STD_LOGIC;
    cfgclk : OUT STD_LOGIC;
    cfgmclk : OUT STD_LOGIC;
    eos : OUT STD_LOGIC;
    preq : OUT STD_LOGIC;
    ip2intc_irpt : OUT STD_LOGIC
  );
END system_basic_axi_quad_spi_0_0;

can I instantiate like this:

Code:
OBUFT #(

.IOSTANDARD("DEFAULT"),

) OBUFT_inst (
.O( io0_o ),
.I(XADC_GPIO_0), 
.T( io0_t) 
);

If so, where to connect io0_i?
 

Attachments

  • obuft.JPG
    obuft.JPG
    24.9 KB · Views: 93

Hi,
I have UART Terminal for my project to control the program like setting IP address, UDP port etc from terminal and also to see the output (printf function) of the program on the terminal.
Now I would like to replace this task of UART with SPI.

and it's not clear to me how to proceed?
The SPI module you are trying to add won't support what you want to do. The SPI module is a MASTER ONLY module, a master on the AXI controls the slave interface of the Quad SPI to control a master SPI to communicate with an external slave SPI. You want to use this as a terminal to control the FPGA which won't work.

You would need a USB (or something) to a SPI master widget along with a SPI SLAVE ONLY module in your FPGA to support what you want to do.

- - - Updated - - -

Also the IOBUFT doesn't need to be instantiated.
code that assigns a pin with a signal or Z will infer a tristate buffer.

Code VHDL - [expand]
1
io_pin_name <= internal_signal_o when internal_signal_t = '0' else 'Z';


or something like that (I'm primarily a Verilog coder)

- - - Updated - - -

Another option could be to use the Vivado debug tools to insert the JTAG to AXI master IP into the design, which allows you to read/write addresses in a design via the xilinx platform cable using Tcl commands. Of course this doesn't allow you to make a printf type thing, but neither does SPI.
 

The SPI module you are trying to add won't support what you want to do. The SPI module is a MASTER ONLY module, a master on the AXI controls the slave interface of the Quad SPI to control a master SPI to communicate with an external slave SPI. You want to use this as a terminal to control the FPGA which won't work.

You would need a USB (or something) to a SPI master widget along with a SPI SLAVE ONLY module in your FPGA to support what you want to do.
Hi,
I don't have USB or something like that at the moment. Could you please clarify me how much of UART work is practically possible via SPI? Can I atleast read and write the register of the program via SPI?
 

Hi,
I don't have USB or something like that at the moment. Could you please clarify me how much of UART work is practically possible via SPI? Can I atleast read and write the register of the program via SPI?

You can read write registers in your FPGA (the SPI slave) using a SPI master, but unlike a UART you won't be able to use SPI as a printf type output as the master needs to initiate transfers not the slave.
 
Apologies for my pointing you to OBUF in #12.
From #13 I think you need and IOBUF (bidirectional buffer) as you have the signals.
io0_i : IN STD_LOGIC;
io0_o : OUT STD_LOGIC;
io0_t : OUT STD_LOGIC;
In ug471 it is found in page 39.
The Figure 1-24, the "IO to/from device pad" should be the FPGA pin.

I don't know what you are trying to achieve, but remember the quad_spi you are using is a master. It needs to be connected to SPI slaves. If you are not connecting any slaves, then all you can do from your uBlaze is write to the quad_spi control_registers or read from the status registers. How to read/write those using a simple C code I have shown in #10.

As ads-ee has said printf like functionality is not possible with SPI.

- - - Updated - - -

So answering your question...
This means at least for this purpose how I am proceeding above is right?
If you connect an IO buffer b/w the quad_spi ports and an FPGA IO pin then you are good to go.
 
Hi,
I am supposed to use SPI as a slave and configured as mentioned in pg 153 page 84 (uncheck Enable master mode). I would like to know theoritically what will be difference when working as slave compared to working as master?

Can I say I even don't need to configure access to my program as SPI slave to be controlled from external SPI Master rather just provide access to the register(GPIO pin) to external master?
 
Last edited:

I am supposed to use SPI as a slave and configured as mentioned in pg 153 (uncheck Enable master mode).
It is written in the spec.
Enable Master Mode : Enables master SPI mode when checked, slave SPI mode when not checked. The enable master mode parameter is applicable only in standard SPI mode. In dual or quad SPI mode, only master SPI mode is supported.
i.e. As I understood it - If you are using only 1 SPI channel then this core from Xilinx can also be used as a slave device (1 SPI master can be connected to it). If you want to use more channels, then this core will only act as master device and all connected SPI devices will be slaves.

I would like to know theoritically what will be difference when working as slave compared to working as master?
Now its deviating from the original topic. Please create a new thread for your new Q.
Also do some search yourself. Understanding a master-slave function is a trivial thing.

Can I say I even don't need to configure access to my program as SPI slave to be controlled from external SPI Master rather just provide access to the register(GPIO pin) to external master?
To answer that, I have to read the spec in details as to how it behaves. Sorry don't have time for that!
 

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