Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

x51 memory share with ext dev

Status
Not open for further replies.
U

userx51

Junior Member level 2
Joined
Apr 21, 2013
Messages
20
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,432
Hello,
I am very new to cx51 world. How to make external device like FPGA to have access to external memory of cx51?. FPGA should see any update made to the external memory of 8051.
 

The external memory address , data and control signals controlled by a multiplexer , with 8051 and fpga accessing the same.

or, dual port ram is another option.
 

those are the only ways?.
 

Hi,

Wire all the address, data and control lines through fpga.
UC --> FPGA --> SRAM

Klaus
 

KlausST said:
Hi,

Wire all the address, data and control lines through fpga.
UC --> FPGA --> SRAM

Klaus
Click to expand...

Then the multiplexer mentioned in post #2 would reside inside the FPGA instead of an external part. The only issue might be the latency or delay due to the FPGA, which may require more wait states for reads.
 

Hi,

My answer in post#4 is ONE possible way.

The delay in an FPGA usually is short enough not to hurt an ´51 memory access.

I don´t know what the ´51 access cycle time is, but modern "slow" SRAM have 70ns or 55ns access time.

Klaus
 

KlausST said:
I don´t know what the ´51 access cycle time is, but modern "slow" SRAM have 70ns or 55ns access time.

Klaus
Click to expand...

not much of a performance improvement since I used asynchronous SRAM back 25+ years ago, back then fast SRAM was 35 ns. I would have hoped with the current technology a slow modern SRAM on a modern process would be <<< 35 ns today. :shock:
 

Hi,

Sorry I meant microcontroller cycle time.
Out of curiosity I checked ATMEL AT89C51 datasheet.
Clock up to 60MHz. 6 clock cycles for external memory access (cycle time) = 100ns. So a 70ns rated SRAM should be OK for this microcontroller.

Klaus
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top