lady_vlsi
Newbie level 1
Hi! I really need help, and it's pretty urgent because i must submit a project and i'm late already.
1. how should i bias:
3T GC-eDRAM (only NMOS devices)
2T GC-eDRAM (write is NMOS, read is PMOS)
in order to measure the static power consumption?
and more important:
2. How do I actually measure the static power consumption??
I'm using cadence virtuoso function: pwr with a transient response, and when i look at the graphic results, the power keeps changing all the time because of the storage node (i modeled it with a capacitor). so how am i supposed to measure static power consumption??
so desperate
thanks!
1. how should i bias:
3T GC-eDRAM (only NMOS devices)
2T GC-eDRAM (write is NMOS, read is PMOS)
in order to measure the static power consumption?
and more important:
2. How do I actually measure the static power consumption??
I'm using cadence virtuoso function: pwr with a transient response, and when i look at the graphic results, the power keeps changing all the time because of the storage node (i modeled it with a capacitor). so how am i supposed to measure static power consumption??
so desperate
thanks!