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Desperate for help: GC-eDRAM power consumption measurement using cadence virtuoso

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lady_vlsi

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Hi! I really need help, and it's pretty urgent because i must submit a project and i'm late already.

1. how should i bias:

3T GC-eDRAM (only NMOS devices)
2T GC-eDRAM (write is NMOS, read is PMOS)

in order to measure the static power consumption?

and more important:
2. How do I actually measure the static power consumption??
I'm using cadence virtuoso function: pwr with a transient response, and when i look at the graphic results, the power keeps changing all the time because of the storage node (i modeled it with a capacitor). so how am i supposed to measure static power consumption??

so desperate :(

thanks!
 

In general, you bias a P-device On by pulling the gate low (or by connecting its gate to ground). Bias it Off by pulling the gate high, as high as its supply voltage.

To measure current consumption, install a low-ohm resistor inline with the power supply. Measure voltage across the resistor and this lets you calculate current draw.

Since you say the power is changing all the time, you need to average it. There is the idea of arranging an inductor and capacitor as a low-pass filter. The effect is to make the waveform smooth (instead of like a city skyline). Values are not necessarily easy to calculate, but once you have them adjusted it is easy to read the average current drawn by your device.

I am not familiar with Cadence Virtuoso. For all I know it has a command which provides the function you're asking about.
 

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