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concatenation of Matrix element in verilog

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Hi,
I have:

Code: 
localparam mem_x_size = 240; 
localparam mem_y_size = 128;
reg [0:0] Y_waveform[0:mem_x_size-1][0:mem_y_size-1];
reg [9:0] rx_ds1a_reg=10'b0;
reg [8:0] x_index= 9'b0;
reg [7:0] y_index=8'b0;

and I want to cancatenate
Code: 
always(@clk)
begin
 rx_ds1a_reg <= {Y_waveform[x_index][y_index], 9'b100000000} ;
end

but why cancatenating part is not synthesizable?
 

Because rx_ds1a_reg is a 1-D array.

See what is declared for Y_waveform array!
 

Once again your treating Verilog as software. A 2D array does not necessarily translate to a memory. Many times you will end up with a large array of FFs., which maybe is okay in this case as the entire array is single bits and only 240x128.

You really need to be aware you are designing a digital hardware design and what each line of code represents in hardware.

There is also the issue with always @(clk) which does not represent any known FF type, as the code will respond to the level changes of clk. Use posedge keyword for FFS, unless you intentionally want a latch, then you will need to add the clk in an if structure to define the high level and low level behavior. Also rename rx_ds1a_reg to rx_ds1a_latch so others and you will know you intended a latch to be implemented. Just be prepared to justify the use of a latch.
 

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