Layout design for ESD

Hi......

Can anyone explain about basics of ESD & ESD protection methodologies in analog layout IC design.please share if have any documents.

Thanks in advance.

Hi,

do you have access to google or other internet search engines?
You will find a lot of documents.
Best is to look at the big analog IC manufacturers.

Klaus

For any given technology, the manufacturer will almost always
provide you "blessed" ESD protection cells, usually a whole
library of them (generally bundled with the pad stuff). You
do not want to invent anything you don't have to. Cases
where you would, are things like (say) an analog pad in a
"digital" technology, pads that must tolerate some outside-
the-rails operation and so on.

The important thing is to follow the proven detailed layout
styles, so either you don't fail or these details aren't your
fault. There should be foundry specific documents made
available to you, if you're doing it for real.

Your failure modes are overvoltage and overcurrent. The
first really goes to shunt and clamp effectiveness, the whole
pin-pin current-loop mess has to have every entry and exit
under control. Exhaustive simulation is a good thing to use,
provided that you are given, or can make, realistic ESD
element models (not a good blind bet, laziness abounds).
On my chips I build the I/O ring as its own construct and
do pin-pin zaps using my own little "stinger" cells and
nested parametric analysis loops, collect the pin voltages
and criticize the pin excursions (some of this requires a
bit of digging-in, absolute voltage is not the same as the
worst case individual device stress).

Current you deal with by fat metal, more contacts and
vias than you think you'd ever need, by not doing stupid
things like making clamp entry and exit at the same end,
not-cheating on silicide pullback rules (which cost you
series resistance) and not trying to use core devices
in ESD applications (lacking silicide pullback entirely).
!silicide equals a "ballast resistor" that forces more
uniform conduction (at the cost of density) to keep
"hot spots" from hogging current and getting killed.

There are textbooks devoted to this specifically. I'd look
for a newer one if you're working in newer nodes, the
design for very low voltages is difficult in its own ways
(but try making a 100V pin protection that stands up to
4kV HBM, which means about 300W peak power, some
time).

saha.123 said:

Hi......

Can anyone explain about basics of ESD & ESD protection methodologies in analog layout IC design.please share if have any documents.

Thanks in advance.

Click to expand...

You need to adopt an "outside in" approach.

All ESD threats come from the outside, mainly circuit parts that can be touched, mainly switches, buttons, displays etc....
If these are metallic, or made of some conducting material, then you are off to a good start. Plastic enclosures can be sprayed with an internal conducting layer, or conductive foils can be glued inside.

Other ESD threats come from external connections, plugs sockets, PCB edge connectors, and so on. Individual exposed pins each need to be thought about individually as far as impedance and ESD susceptibility to damage and the possible need for voltage clamping.

Nodes within a circuit that have no external connections are only likely to suffer damage during manufacturing or service, and that should be of no real concern if staff are trained in safe handling techniques. That is not a thing for the designer to really worry too much about.

So your very first priority should be a robust outside fully enveloping conductive enclosure, and any electronic parts that penetrate that enclosure.
That is the ideal place to stop ESD.

For IC design you have to expect no help from outside, and
make the part tough enough for your customer to handle and
for your customer to avoid one penny more of BOM expense.
So you see things like 10kV+ HBM ratings on USB and HDMI
chips, far outside handling-ESD requirements and all about
nobody having to pay for pin protection at the next level up.
That's just the dues and if you don't, your competition will.
Show up to that party with a story about how they should
design their enclosure and you'll be laughed out of the room
before the donuts arrive.

As a retired equipment designer, Your first line of defence against ESD is still always going to be the outer containing hardware.

Neglect that, and you are really going to face a challenge later at the testing stage when its really too late to make major changes.

So we saved a penny at the design stage and it cost us thousands to fix late in the development cycle.
That usually quickly stop the laughter.

Show up to that party with a story about how they should
design their enclosure and you'll be laughed out of the room

Click to expand...

I disagree with that.
The design "team" should be made fully aware of:
Electrical safety, EMC, and ESD requirements, and provided with suitable options if the project is to have any hope of eventual success.

All of that may be true of larger hardware, but the IC designer
can seldom be assured that any of it will be there for them
and their part has to meet the numbers regardless.

Yes, you are quite right.
The IC designer is faced with some practical limit to what he can put into an IC with regard to shrinking pin pitches, shrinking internal geometries, and realistic peak pulse discharge power dissipation.

I still believe its the job of the circuit designer to provide a robust reliable circuit design that does not require very much protection right at chip level, beyond what is needed for normal safe handling practice.
But more is always better !