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Verilog code Error in ISIM

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Rustum

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Hi all,,
I am getting the following error in mode code.What are the possible causes for it?
Code: 
HDLCompiler:31 - "C:/Users/gyan.CYSEMI/Documents/PSoC Creator/SDIO_MASTER/SDIO_M.v" Line 123: <idle> is already declared.
ERROR:HDLCompiler:31 - "C:/Users/gyan.CYSEMI/Documents/PSoC Creator/SDIO_MASTER/SDIO_M.v" Line 136: <read_block> is already declared.
ERROR:HDLCompiler:31 - "C:/Users/gyan.CYSEMI/Documents/PSoC Creator/SDIO_MASTER/SDIO_M.v" Line 142: <read_block_wait> is already declared.
ERROR:HDLCompiler:806 - "C:/Users/gyan.CYSEMI/Documents/PSoC Creator/SDIO_MASTER/SDIO_M.v" Line 143: Syntax error near "and".
ERROR:HDLCompiler:31 - "C:/Users/gyan.CYSEMI/Documents/PSoC Creator/SDIO_MASTER/SDIO_M.v" Line 153: <read_block_data> is already declared.
ERROR:HDLCompiler:31 - "C:/Users/gyan.CYSEMI/Documents/PSoC Creator/SDIO_MASTER/SDIO_M.v" Line 167: <read_block_crc> is already declared.
ERROR:HDLCompiler:31 - "C:/Users/gyan.CYSEMI/Documents/PSoC Creator/SDIO_MASTER/SDIO_M.v" Line 173: <send_cmd> is already declared.
ERROR:HDLCompiler:31 - "C:/Users/gyan.CYSEMI/Documents/PSoC Creator/SDIO_MASTER/SDIO_M.v" Line 187: <receive_byte_wait> is already declared.
ERROR:HDLCompiler:31 - "C:/Users/gyan.CYSEMI/Documents/PSoC Creator/SDIO_MASTER/SDIO_M.v" Line 205: <receive_byte> is already declared.
ERROR:HDLCompiler:31 - "C:/Users/gyan.CYSEMI/Documents/PSoC Creator/SDIO_MASTER/SDIO_M.v" Line 220: <write_block_cmd> is already declared.
ERROR:HDLCompiler:31 - "C:/Users/gyan.CYSEMI/Documents/PSoC Creator/SDIO_MASTER/SDIO_M.v" Line 233: <write_block_init> is already declared.
ERROR:HDLCompiler:31 - "C:/Users/gyan.CYSEMI/Documents/PSoC Creator/SDIO_MASTER/SDIO_M.v" Line 238: <write_block_data> is already declared.
As i have declared the states as parameter but really dont know why it is happening?

Second query is---
can i write the condition in if statement like below-


"if(sclk_sig==1 and miso==0)"-------it is throwing an error.


Please help me!!!
 

As for the second question, logical and operator in Verilog is &&.

Regarding first, presume you can see that the parameters are defined twice. We can't - without the code.
 

Rustum said:
"if(sclk_sig==1 and miso==0)"-------it is throwing an error.
Click to expand...

FvM already answered this, but I thought I would show the compare contrast with Verilog/VHDL

VHDL:
Code VHDL - [expand]
1

IF (sclk_sig = '1' AND miso = '0')


Verilog:
Code Verilog - [expand]
1

if (sclk_sig && !miso)


VHDL coders typically write Verilog code like this:
Code Verilog - [expand]
1
2

// lets make Verilog as verbose as VHDL (for no good reason)
if (sclk_sig == 1'b1 && miso == 1'b0)


- - - Updated - - -

Regarding the first, are there any `include files that might already have the parameters defined?
 

Code Verilog - [expand]
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    19:18:28 09/24/2016 
// Design Name: 
// Module Name:    SDIO_M 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module SDIO_M(
    input clk,
    input [7:0] din,
    input reset,
    input dm_in,
    input wr,
    input rd,
    input miso,
    output reg mosi,
    output reg cs,
    output reg sclk,
    output reg [7:0] dout
    );
parameter [4:0] rst=5'd0,
                init=5'd1,
                     cmd0=5'd2,
                     cmd55=5'd3,
                     cmd41=5'd4,
                     poll_cmd=5'd5,
                     idle=5'd6,
                     read_block=5'd7,
                     read_block_wait=5'd8,
                     read_block_data=5'd9,
                     read_block_crc=5'd10,
                     send_cmd=5'd11,
                     receive_byte_wait=5'd12,
                     receive_byte=5'd13,
                     write_block_cmd=5'd14,
                     write_block_init=5'd15,
                     write_block_data=5'd16,
                     write_block_byte=5'd17,
                     write_block_wait=5'd18;
reg [4:0] state,return_state;
integer byte_counter=515;
integer bit_counter=160;
reg sclk_sig;
reg [55:0] cmd_out;
reg [7:0] recv_data;
reg [31:0] address;
reg cmd_mode=1;
reg data_mode=1;
reg response_mode=1;
reg [7:0] data_sig=8'h00;
always @(posedge clk or reset)
    begin 
       data_mode<=dm_in;
        if(reset)
          begin
            state<=rst;
             sclk_sig<=0;
             end
             else begin
        case(state)
           rst:begin
                  sclk_sig<=0;
                    cmd_out<=0;
                    address<=0;
                    byte_counter=0;
                    cmd_mode<=1;
                    response_mode<=1;
                    bit_counter=160;
                    cs<=1;
                    state<=init;
                    end
                    
          init:begin
                if(bit_counter==0)
                    begin
                       cs<=0;
                        state<=cmd0;
                        end
                    else begin
                       bit_counter<=bit_counter-1;
                        sclk_sig<=~sclk_sig;
                        end
                    end
        cmd0:begin
               cmd_out<=56'hff400000000095;
                 bit_counter<=55;
                 return_state<=cmd55;
                 state<=send_cmd;
                 end
        cmd55:begin
                cmd_out<=56'hff770000000001;
                 bit_counter<=55;
                 return_state<=cmd41;
                 state<=send_cmd;
                 end
        cmd41:begin
                cmd_out<=56'hff690000000001;
                 bit_counter<=55;
                 return_state<=poll_cmd;
                 state<=send_cmd;
                 end
      poll_cmd:begin
                  if(recv_data[0]==1'b0)
                       begin
                          state<=idle;
                         end
                        else begin
                          state<=cmd55;
                            end
            idle:begin
                   if(rd)
                       begin
                          state<=read_block;
                          end
                    else if(wr)
                        begin
                            state<=write_block_cmd;
                             end
                    else begin
                          state<=idle;
                            end
                    end
        read_block:begin
                     cmd_out<={8'hff,8'h51,address,8'hff};
                         bit_counter<=55;
                         return_state<=read_block_wait;
                         state<=send_cmd;
                         end
read_block_wait:begin
                  if(sclk_sig && !miso)
                            begin
                               state<=read_block_data;
                                byte_counter<=511;
                                bit_counter<=7;
                                return_state<=read_block_data;
                                state<=receive_byte;
                                end
                        sclk_sig<=~ sclk_sig;
                        end
read_block_data:begin
                 if(byte_counter==0)
                        begin
                          bit_counter<=7;
                          return_state<=read_block_crc;
                          state<=receive_byte;
                          end
                        else begin
                           byte_counter<=byte_counter-1;
                            return_state<=read_block_data;
                            bit_counter<=7;
                            state<=receive_byte;
                            end
                        end
read_block_crc:begin
                 bit_counter<=7;
                      return_state<=idle;
                      address<=address+12'h200;
                      state<=receive_byte;
                      end
      send_cmd: begin
                  if(sclk_clk)
                           begin
                               if(bit_counter==0)
                                  begin
                                    state<=receive_byte_wait;
                                    end
                            else begin
                               bit_counter<=bit_counter-1;
                                cmd_out<={cmd_out[54:0],1'b1};
                                end
                                sclk_sig<=~sclk_sig;
                                end
                        end
receive_byte_wait:begin
                    if(sclk_sig)
                              begin
                                  if(!miso)
                                   begin
                                      recv_data<=8'h00;
                                      end
                                      end
                            if(!response_mode)
                               begin
                                    bit_counter<=3;
                            end
                            else begin
                               bit_counter<=6;
                                end
                            state<=receive_byte;
                            sclk_sig<=~sclk_sig;
                            end
        receive_byte: begin
                         if(sclk_sig)
                                begin
                                   recv_data<={recv_data[6:0],miso};
                                    end
                            if(bit_counter==0)
                              begin
                                state<=return_state;
                                 dout<={recv_data[6:0],miso};
                                 end
                            else begin
                                bit_counter<=bit_counter-1;
                                 end
                        sclk_sig<=~sclk_sig;
                        end
    write_block_cmd:begin
                      cmd_mode<=1;
                            if(!data_mode)
                              begin
                                cmd_out<={8'hff,8'h59,address,8'hff};
                                 end
                            else begin
                              cmd_out<={8'hff,8'h58,address,8'hff};
                                end
                            bit_counter<=55;
                            return_state<=write_block_init;
                            state<=send_cmd;
                            end
    write_block_init:begin
                       cmd_mode<=0;
                             byte_counter<=515;
                             state<=write_block_data;
                             end
    write_block_data: begin
                        if(byte_counter==0)
                                begin
                                   state<=receive_byte_wait;
                                    return_state<=write_block_wait;
                                    response_mode<=0;
                                    end
//                              else begin
                                    if(byte_counter==2 or byte_counter==1)
                                       begin
                                           data_sig<=8'hff;
                                            end
//                              else begin 
                                if(byte_counter==515)
                                    begin
                                        if(!data_mode)
                                          begin
                                              data_sig<=8'hfc;
                                                end
                                        else begin
                                            data_sig<=8'hfe;
                                             end
                                             end
//                                           end
//                                           end
                                        else begin
                                              data_sig<=din;
                                                end
                                        bit_counter<=7;
                                        state<=write_block_data;
                                        byte_counter<=byte_counter-1;
                                        end
                                    
                            
            write_block_byte: begin
                                
                                          if(sclk_sig)
                                            begin
                                               if(bit_counter==0)
                                                   begin
                                                     state<=write_block_data;
                                                     end
                                            else begin
                                                 data_sig<={data_sig[6:0],1'b1};
                                                  bit_counter<=bit_counter-1;
                                                  end
                                                  end
                                                  sclk_sig<=~sclk_sig;
                                                  end
        write_block_wait:begin
                           response_mode<=1;
                                 if(sclk_sig)
                                   begin 
                                      if(miso)
                                         begin
                                            if(!data_mode)
                                               begin
                                                   state<=write_block_init;
                                                end
                                                end
                                                end
                                        else begin
                                            address<=address+12'h200;
                                             state<=idle;
                                             end
//                                          end
//                                          end
                                             sclk_sig<=~sclk_sig;
                                             end
//              default: begin 
//                          state<=idle;
//                              end
                endcase
        
                                        
    end
end 
                                                 
assign sclk=sclk_sig;
assign mosi=(cmd_mode)?cmd_out[55]:data_sig[7];                                       
                    
endmodule
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Hi friends,
Thank you for your response but I am still not able to resolve the problem.
I have attached my project,Please help to fix my problem.
 
Last edited by a moderator:

Syntax errors:
line 64: wrong event specifier
line 66: assignment outside event condition not allowed
after line 122: missing end
246: "or" isn't a Verilog operator

Seems like Xilinx tools syntax check doesn't lead you to the error locations, or you aren't able to read the messages.

"<idle> is already declared" e.g. is caused by the missing end statement. You should wonder why the "poll" case expression is accepted and "idle" isn't.
 

Hi,

What is the error description now?

Is it the same line: "if (sclk_sig && !miso)"?

If not: Please post the error description.

Klaus
 

Hi friends,
Thank you so much for your support.
I got some success and able to fix the issues.

Now I have one doubt stated below,Kindly help me to fix it out-
--------------------------------
output reg mosi,
output reg cs,
output reg sclk,
output reg [7:0] dout
-----------------------------------
When I used the signal declaration like in above lines of my project code,I got the following errors-
----------------------------
Error:HDLCompiler:329 - "C:/Users/gyan.CYSEMI/Documents/PSoC Creator/SDIO_MASTER/SDIO_M.v" Line 317: Target <sclk> of concurrent assignment or output port connection should be a net type.
ERROR:HDLCompiler:329 - "C:/Users/gyan.CYSEMI/Documents/PSoC Creator/SDIO_MASTER/SDIO_M.v" Line 318: Target <mosi> of concurrent assignment or output port connection should be a net type.
ERROR:HDLCompiler:598 - "C:/Users/gyan.CYSEMI/Documents/PSoC Creator/SDIO_MASTER/SDIO_M.v" Line 21: Module <SDIO_M> ignored due to previous errors.
Verilog file C:/Users/gyan.CYSEMI/Documents/PSoC Creator/SDIO_MASTER/SDIO_M.v ignored due to errors

Process "Behavioral Check Syntax" failed
------------------------------------

Then I changed my code snippet like below-
----------------------
output mosi,
output reg cs,
output sclk,
output reg [7:0] dout
------------------------------------
NO ERROR!!!

Please clarify it.

Thank you so much!!!
 

I have my compiler set to System Verilog syntax and don't get the respective error. It's a kind of Verilog legacy problem.

The error message is quite clear, I think. In classical Verilog, it's not allowed to make a continuous assignment to a net type. You are doing this in line 316 and 317.
 

By removing the reg from your definition of sclk, it defaults to a wire. Sclk must be a wire because you use the assign statement to assign sclk to sclk_sig. Assign is only used for wires.

r.b.
 

Right this is all quirky verilog stuff that you just need to become familiar with.

There are different syntax's for assigning a register versus assigning a wire. If you switch between the two, as you did by adding/removing the reg, you also need to change every place you assign that signal.

Registers get assigned within a begin/end, wires get assigned with 'assign'.



Note that you're lucky you're getting these messages. There is a really nasty bug in ISE/ISIM where declaring a regular signal as a register and then assigning it as a was a wire causes a "FATAL ERROR:ISim". For example the following inserted anywhere causes a FATAL ERROR (for me every time anyway):

Code: 
	reg testing1;
	assign testing1 = 1'b0;
 

asdf44 said:
Registers get assigned within a begin/end, wires get assigned with 'assign'.
Click to expand...

Uh, begin-end, not true. Begin-end defines a block. reg types get assigned within procedural blocks, which if there are more than one statements can be between begin-end statements.

This is perfectly legal Verilog and does not use begin-end.
Code Verilog - [expand]
1
2

reg q;
always @ (posedge clk) q <= d;
 

And just to make sure everyone is clear, the reg type doesnt always have to infer a register:

Code Verilog - [expand]
1
2
3

reg reg_is_really_a_wire;
 
always @(*) reg_is_really_a_wire <= a;
 

TrickyDicky said:
And just to make sure everyone is clear, the reg type doesnt always have to infer a register:

Code Verilog - [expand]
1
2
3

reg reg_is_really_a_wire;
 
always @(*) reg_is_really_a_wire <= a;
Click to expand...

To be even more clear ;-)

The signal reg_is_really_a_wire is within a procedural block (the always) and therefore requires that you use the reg type. Note, SV has a much more lax logic type that can be used in procedural blocks and in assigns.
 

ads-ee said:
To be even more clear ;-)

The signal reg_is_really_a_wire is within a procedural block (the always) and therefore requires that you use the reg type. Note, SV has a much more lax logic type that can be used in procedural blocks and in assigns.
Click to expand...

Actually, in SV, every variable type can be put into procedural blocks or assigned (but not both), except reg. reg can only be used in procedural assignments. anything on the LHS in an assign are implicitly declared as wire.

wire in SV becomes a way to declare a net, rather than being a type in itself. a wire can have any data type (except reg).
 

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