Synthesis tool - meeting hold time constrains

Hello,

How do synthesis tools try to meet hold time requirements ?
Is it done via placement only - or will they add combinatoric delay elements in the way of problematic paths ?

The placer uses pass throughs, i.e. either a dedicated path through a Slice/ALM etc or a LUT. I've never seen these added by the synthesis tool.

shaiko said:

How do synthesis tools try to meet hold time requirements ?
Is it done via placement only - or will they add combinatoric delay elements in the way of problematic paths ?

Click to expand...

I'm not sure, but I don't think the tool will do anything. If you have a hold time issue, the problem is with your design because you have most likely used an internally generated clock based on logic or you have a clock domain crossing.

If you use a synchronous design technique rather than gated clocks, the clock will be routed everywhere it needs to go and the FPGA supplier can guarantee that the clock input will be there with sufficient margin that there can be no hold time problem. When you have a clock domain crossing, you need to insure that you are properly synchronizing to handshake across the clock domain crossing which means that at the actual flip flops where the crossing occurs, you should be flagging that particular path(s) as a multi-cycle path. So, if you use these techniques, then hold time will never be an issue which means there would be no need for the synthesis tool to ever optimize in order to improve hold time.

Kevin Jennings

There are two cases where hold violations occur, at least in my experience. The first is on IO, which should be expected. The second is with hard IP blocks -- GTX tiles, EMACs, etc...

However, hold errors in the latter case are more likely to be a result of a fast-fail that wasn't properly reported. Basically, the tools had so many issues with previous steps that they decided to give up. As a result, no attempts were made to fix hold violations. In this case, the hold violations appear to be an issue, but actually are not. When you see hold violations, make sure to check if the tools have mentioned that they have attempted to fix hold violations.