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Fixing set up violation in feedback path

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biju4u90

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Suppose I am having a design in which the Q output of an FF is fed back to the D input of the same FF through some combinational logics. If I am having set up violations in this situation, how can I fix it? Insteda of having set up violations, if I am having hold violations, how can I fix them?? What if I have both set up and hold violations??
 

biju4u90 said:
Suppose I am having a design in which the Q output of an FF is fed back to the D input of the same FF through some combinational logics. If I am having set up violations in this situation, how can I fix it? Insteda of having set up violations, if I am having hold violations, how can I fix them?? What if I have both set up and hold violations??
Click to expand...

setup violation means the path is too long, that simple. makes no difference that it is a feedback or normal path.
hold violation means the path is too short, that simple. makes no difference that it is a feedback or normal path. you can fix it by adding delay elements to it.

one caveat of these scenarios is that capture/launch clock are always the same, so you can't leverage useful skew in any way.
 
Realistically you're never going to see hold violations for that situation where the source and destination flip-flip (and therefore clock) are the same. Hold time violations would be far more common for inputs coming from a different (and therefore potentially skewed) synchronous clock (an async clock may of course create hold violations but won't be analyzed by timing and needs proper cross-domain design).

Set-up violations are more common and result from you asking the device to do too much work in one clock cycle. You need to reduce the overall workload or break it into smaller pieces (with registers in between), or increase the clock period. Most tools will help you visualize the problematic path to do this.
 
If I am having set up violations in this situation, how can I fix it?
Click to expand...

As a front-end logic design engineer I insert re-timing flops on the path, if the design allowa it (try to do an operation in two clock cycles instead of one). The newly inserted flop will reduce the long path.
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To address setup time violations, you can:

Use larger/stronger cells to drive paths with high capacitance, which can reduce the time needed to transition on sluggish net.
Adjust the skew of the clock to the start or endpoint of the path which is violating. (time borrowing).
Move gates around to make the total distance between different cells in the violating path smaller (less capacitance to drive = faster transitions)
Insert retiming flops on the path, if the design will allow for it (try to do an operation in two clock cycles instead of one)
Reduce the overall clock frequency.

For hold time violations:

Skew the clock to the start/endpoint (reverse of how to fix setup) to make the endpoint clock arrive earlier.
Insert cells along the path to increase the propogation time (insert chains of buffers)
Reduce the drive strength of cells on the path to make the transition time increase.
 
dpaul said:
As a front-end logic design engineer I insert re-timing flops on the path, if the design allowa it (try to do an operation in two clock cycles instead of one). The newly inserted flop will reduce the long path.
-----------------------------------------------------------------------------------------------


To address setup time violations, you can:

Use larger/stronger cells to drive paths with high capacitance, which can reduce the time needed to transition on sluggish net.
Adjust the skew of the clock to the start or endpoint of the path which is violating. (time borrowing).
Move gates around to make the total distance between different cells in the violating path smaller (less capacitance to drive = faster transitions)
Insert retiming flops on the path, if the design will allow for it (try to do an operation in two clock cycles instead of one)
Reduce the overall clock frequency.

For hold time violations:

Skew the clock to the start/endpoint (reverse of how to fix setup) to make the endpoint clock arrive earlier.
Insert cells along the path to increase the propogation time (insert chains of buffers)
Reduce the drive strength of cells on the path to make the transition time increase.
Click to expand...

two comments:
a) you are mistaking retiming with multicycle.
b) clock tree OPT (useful skew) cannot help paths that start & end on the same flop, which is what the OP asked.
 

Suppose I am having a design in which the Q output of an FF is fed back to the D input of the same FF through some combinational logics.
Click to expand...

Right..............I missed it!
 

asdf44 said:
Realistically you're never going to see hold violations for that situation where the source and destination flip-flip (and therefore clock) are the same.
Click to expand...

Why?? When the combinational delay in the feedback path is very small, it may result in hold violations, right?
 

It may, although unlikely. This is not the typical case for hold violations.
 

biju4u90 said:
Why?? When the combinational delay in the feedback path is very small, it may result in hold violations, right?
Click to expand...

Well have you checked real life hold times in your FPGA? A quick look at my latest timing report shows a hold requirement of 0.000ns.

There is a good reason for this which is that it's quite common to have very little combinational logic in a circuit (for example a shift register has none) so FPGAs (and discrete FF's) have to be designed for this. Low hold times (zero or even negative) are quite common.

Given this its quite difficult to run into hold violations within a single domain.
 

I created this post some time ago with diagrams that delved into the hold time and how it affects timing. It also touched on how tools would conceptually have an easier time to meet a setup time then later fix any hold time violations by adding extra delay without affecting the maximum clock frequency attainable.

asdf44 said:
Given this its quite difficult to run into hold violations within a single domain.
Click to expand...
Not true, hold times can definitely occur and they get fixed (look at the log files of a P&R run). These violations are almost always due to clock skew of 100 of ps.
 

Technically speaking, you are both right. You can only have that type of hold violation if the clock tree is skewed. This is more naturally occurring in an ASIC than in FPGAs.
 

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