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[SOLVED] Modulus/reminder operation in FPGA

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mjuneja

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I want to implement modulus or reminder operation in FPGA using VHDL for 2 unsigned nos. I tried using below code.

Code VHDL - [expand]
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process(clk,rst,pxl_1,pxl_2,DV)
begin
    if(rst = '0') then
        pxl_o2 <= (others => '0');
    elsif(rising_edge(clk)) then
        if(DV = '1') then
            pxl_o2 <= std_logic_vector(unsigned(pxl_1) mod unsigned(pxl_2)); 
        end if; 
    end if;
end process;

but got the following error :-
: Operator <MODULUS> must have constant modulo operand.
Click to expand...
Can anyone help me out with some alternate implementation of modulus operation.

Thanks
Madhur
 
Last edited by a moderator:

The question is incomplete. You should show the imported libraries and also tell about the used synthesis tool.

Usage of operator suggests that you are using ieee.numeric_std. Some tools are able to infer a parallel divider for the modulo operation with ieee.numeric_std library, e.g. Altera Quartus. Apparently yours doesn't, so you need to implement a divider component from vendor library.
 

I am using these 2 libraries for my design.

Code: 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

and for synthesis I am using Xilinx XST tool available with ISE project navigator 14.7.
Which parallel divider component are you referring, can you elaborate more on this?
 

Look for Xilinx divider logicore. Maybe there's a way to get simple dividers without pipelining inferred with Xilinx tools as it's possible in Quartus, Xilinx users should tell.
 

Xilinx only supports 2^n divisions, i.e. right shifts.
 
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