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Calibre PEX issue - CC+C extraction

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rameshprakash

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When I use calibre to extract the circuit (with CC+C option) - I see a big intrinsic cap (close to 300fF) for a pmos bias node (biasp to VSS) . The CC between biasp to VSS node is negligible (<<0.1fF) . My question, usually the pmos bias node parasitics should be referenced to VDD (nwell beneath the metal-poly connection).

Do I have to change any settings in Calibre PEX to fix this issue?

Regards,

Ram
 

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