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Parasitic effect in ASIC manual layout

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preethi19

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Hi i have done pure analog layout and did the parasitic extraction too. I can understand parasitic extraction is done to obtain the parasitics that occur as a result of the layout design which we need to minimise. I am learning about digital design layout using encounter. i understand the same routing wires, spacing of blocks can create parasitics. But in a digital design there are many number of gates. How is it possible to check and correct for so many net connections??? I'm learning the process so can anyone pls help!!! Thanks:)
 

Verification tools (extract, and LVS) automate this task.
Then you redo your verification simulations with the
parasitics-aware extracted netlist. There should be an
orderly supported verification flow which pushes the
net loading back into the digital netlist (or a new one)
for purposes of timing closure. If you are working from
schematics then your timing closure may be in SPICE /
Spectre. A synthesis based flow would use wireload
files along with the netlist in the digital simulator.
 
Hi i have done pure analog layout and did the parasitic extraction too. I can understand parasitic extraction is done to obtain the parasitics that occur as a result of the layout design which we need to minimise. I am learning about digital design layout using encounter. i understand the same routing wires, spacing of blocks can create parasitics. But in a digital design there are many number of gates. How is it possible to check and correct for so many net connections??? I'm learning the process so can anyone pls help!!! Thanks:)

the term parasitics can have different meanings to different folks.
for polygon pushers, they are talking about all the Cs and Rs in a layout, including the gates.
for digital SoC people, it means the interconnect. the parasitics "inside" the cells are captured already in the timing characterization that took place way before, when the .lib files were generated.
 
Thank you all for the reply!!!! Yes i understand for analog we check the polygons for parasitic R and C. But i don't understand "parasitic interconnect" in digital. I mean take an analog layout wen we lay the transistor we get some parasitics. Also when we do routing to connect different cells the wires/ interconnect (metals) cause parasitics. So is this the same interconnect parasitic you are talking about in digital too. Like the R and C in analog.

Also could you kindly explain what does it mean by "parasitics inside the cell". Meaning like what does this parasitic represent other than R and C. becoz take analog or digital, in the end all are made of the metal layers that make up a transistor and interconnecting metals. So what kind of parasitic is der other than R and C for digital cells??? Kindly help pls!!! :)
 

Thank you all for the reply!!!! Yes i understand for analog we check the polygons for parasitic R and C. But i don't understand "parasitic interconnect" in digital. I mean take an analog layout wen we lay the transistor we get some parasitics. Also when we do routing to connect different cells the wires/ interconnect (metals) cause parasitics. So is this the same interconnect parasitic you are talking about in digital too. Like the R and C in analog.

Also could you kindly explain what does it mean by "parasitics inside the cell". Meaning like what does this parasitic represent other than R and C. becoz take analog or digital, in the end all are made of the metal layers that make up a transistor and interconnecting metals. So what kind of parasitic is der other than R and C for digital cells??? Kindly help pls!!! :)

I take it that you are not a digital designer. There are no other parasitics for standard cells, presently it's all modelled as R and C.
Digital design uses standard cells as instances, and then connects these instances with metal wires and vias. The cells and the wires are characterised at different times. All the parasitics inside the cells are captured when the standard cell provider does its own extraction. The parasitics from the interconnect wires are extracted by the ASIC designer at design time.
 
Thank you for the replies! Can you pls list the verification tools used for parasitic extraction? so parasitic extraction is done during LVS so i guess both uses the same tools. Am i right about this?
 

Thank you for the replies! Can you pls list the verification tools used for parasitic extraction? so parasitic extraction is done during LVS so i guess both uses the same tools. Am i right about this?

not the same tools, or not the same version of the tool. digital designs cannot afford to make huge extractions, so the interconnect is modelled as 2D instead of 3D for most routing/timing tasks. At the very end of the flow then you switch to full 3D for signoff.
 

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