Webinar - Struggling with SystemC Modeling. Try-out this faster alternate

SystemC is the standard for SoC exploration and model IP sharing. As the EDA vendors have integrated SystemC with their Verilog/VHDL simulators, the system analysis model can also be used for early verification.

Unfortunately, model construction is very tedious in SystemC, can take months for one IP, and the requirements for architecture exploration is very different from verification. Moreover integrating blocks from different groups is extremely difficult because of differencing data types, abstraction and clocking variations. As a result, a number of system modeling projects fail.

We, at Mirabilis Design, have come up with a library- and script- based that accelerates system modeling and analysis. Using the VisualSim modeling technology, models are constructed graphically using either pre-built IP blocks, script language or existing SystemC modules. With this approach, a fully validated cycle-accurate AXI bus took about 2-3 weeks to construct while a signal- and cycle-accurate DDR3 with timing and power embedded took about a month and a half.

In this Webinar, we will demonstrate the construction of an SoC, how to quickly customize via parameters for a specific implementation, and run large iterations using text files. We will show how to create models using pre-existing blocks and creating custom blocks quickly.

Key Takeaways:

2. Fast model construction
3. Setup models to focus on architecture exploration
4. Learn about VisualSim for system modeling

Date & Time:​

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