UltraGreen
Junior Member level 3
The differential input clock has to be fed to AXI bridge pcie-gen3 for ultrascale, also the same clock pin needs to be fed at MMCM to generate other clocks.
I connected ibufds_GTE3 to the differential clock pins and axi-bridge-pcie3 is driven by output of ibufds_GTE3; this works fine.
But as soon as I connect the same output of ibufds_GTE3 and drive MMCM through bufg . I get the following error:
"ERROR: [DRC 23-20] Rule violation (RTSTAT-2) Partially routed net - 1 net(s) are partially routed"
Help needed, Thanks
I connected ibufds_GTE3 to the differential clock pins and axi-bridge-pcie3 is driven by output of ibufds_GTE3; this works fine.
But as soon as I connect the same output of ibufds_GTE3 and drive MMCM through bufg . I get the following error:
"ERROR: [DRC 23-20] Rule violation (RTSTAT-2) Partially routed net - 1 net(s) are partially routed"
Help needed, Thanks