Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

To implement set_clock_latency defined for memory clcok pins in sdc in CTS

Status
Not open for further replies.
A

argha07

Newbie level 3
Joined
Aug 24, 2016
Messages
3
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
26
Hi ,

I came to know that latency defined in sdc does not get implemented by tool in CTS.

In my case , i have one clock port through which it is distributing to all the memory clock pins as well as sequential flops.

In my constraints i have defined set_clock_latency -0.7 [get_pins full_hierchy_path_to_memory_clock_pin]

What are the switches/command in ICC to honor this latencies during CTS.Please note tool is ICC.

Thanks,
Argha
 

argha07 said:
Hi ,

I came to know that latency defined in sdc does not get implemented by tool in CTS.

In my case , i have one clock port through which it is distributing to all the memory clock pins as well as sequential flops.

In my constraints i have defined set_clock_latency -0.7 [get_pins full_hierchy_path_to_memory_clock_pin]

What are the switches/command in ICC to honor this latencies during CTS.Please note tool is ICC.

Thanks,
Argha
Click to expand...

I think you are getting the concept of latency wrong. When you are doing early estimation or even logical synthesis, you use latency as a placeholder for the actual insertion delay of the clock tree. Later, when implementation is taking place, the latency you set is replaced by the actual obtained latency of the tree.
 

What is the reason for this constraint ?

"set_clock_latency -0.7 [get_pins full_hierchy_path_to_memory_clock_pin] "

If you are doing something to get the timing MET on idea STA report, it mean other clock latencies are "0", and memory_clock latency is "-0.7".
If you realy need that latency skew, you can make the constraint on CTS step. ICC can handle to make that skew later on.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top