Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

CMOS transistors terminology

Status
Not open for further replies.
P

Pavlanto

Guest
Hi,
I read a paper in which i read this sentence:"The supply voltage is 3V to improve the signal swing with
both 3.3V high voltage transistor and 1.2V low voltage transistor used".

What exactly is the 3.3V high voltage transistor and 1.2 low voltage transistor?Where do these voltages refer to?
 

When using a 0.12µm CMOS process, it is possible to make a hybrid transistor with lower Vgs of 1.2 with a 0.12 µm short gate length that permits lower RdsOn with lower CISS and higher fT. The longer gate length enables a higher Vgs for 3.3V operation so that level shifting can be included in the design for logic puposes to enable RF generated from the lower voltage FETs.

This would be useful for RF applications such as SDR, using the higher fT in linear mode of operation using standard CMOS fabrication methods which are much lower cost than GaAs.
 

"I am using a 60nm process. I am running a THA circuit. The up transistors connected to Vdd are called high-voltage transistors and the low transistors connected to the GND are called low voltage transistor. In the photo it is M1-M2-M5-M6 the high voltage and M7-M3-M4-M8 low voltage. What is the difference between the transistors?"


https://obrazki.elektroda.pl/7742034300_1471795108.jpg
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top