Why clock signal should have low transition time?

We are using special buffers and inverters to build the clock tree which have low transition time. What are the problems if clock transition time is high??

same thing with high transition time in regular logic: delay and crosstalk. generally speaking, the higher the delay of a branch of a clock tree, the harder it is to balance it with the rest of the tree.

Has clock transition something to do with the flip flop set up time values?

biju4u90 said:

Has clock transition something to do with the flip flop set up time values?

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yes and no, but that is a different issue.

think of a clock tree that has a single INVX1 driving hundreds of flops. because of all the load seen by the INVX1, it will take a long time for it to transition and your clock tree will be pretty bad. this is what I would call a clock tree with high transition times.

now think of a different scenario where you have one INVX1 at the root, this INVX1 is connect to 4 INVX4, which are connect to 4 INVX16, which finally drive the flops. if you think of it in terms of delay, you added two gates to this path and for sure it will take time for the clock signal to propagate. this additional time is probably negligible compared to the huge transition time of the first case. this would be a better clock tree even if the insertion delay is higher.

ThisIsNotSam said:

yes and no, but that is a different issue.

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How clock transition value effect the set up time of a flip flop? How the set up time of a flip flop is calculated? In the library file, there is no set up time or hold time value of a flip flop specified. How the tool calculates the set up and hold time of a flip flop? On what all factors do the set up and hold time values depend?

biju4u90 said:

How clock transition value effect the set up time of a flip flop? How the set up time of a flip flop is calculated? In the library file, there is no set up time or hold time value of a flip flop specified. How the tool calculates the set up and hold time of a flip flop? On what all factors do the set up and hold time values depend?

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ARE YOU SURE your .lib file has no setup info? look for lines like "timing_type : setup_falling;" on the data input of the flop.

FlipFlop setup time which you see in the report, affected by 2 both FF type and input clock transition.
If I remember correctly, there is a table in .lib file showing that relationship.
You can have a check and confirm this.

slutarius said:

If I remember correctly, there is a table in .lib file showing that relationship.

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Yes, there is. It would be impossible to do digital design not knowing the setup/hold behaviour of the flops.

Yes. There it is. The setup time of the flip flop is calculated as a function of related pin transition and constrained pin transition. Thanks for the help.