fixed point multiply accumulate in VHDL for Xilnx FPGA

Hi All,

I need to implement a tapped FIR filter in a Xilinx FPGA using VHDL . This means that i will need to do fixed point multiplication and addition.
I have read through some of the post on the xilinx and edaforum and not closer to understanding the best way to represent fixed point numbers in VHDL


There seems to be mixed success by using ieee_proposed.fixed_pkg package in Xilnx ISE/Vivado

So my question is to anyone who has successfully done something similar to this is , Do i need to rollout my own fixed point representation ( i.e either make it an integer , or use Q format) [1]
or is ieee_proposed.fixed_pkg widely used for VHDL fixed point operations and i can use this instead.

Any help is much appreciated

References
[1] Article on VHDL fixed point custom implementation : https://www.eetimes.com/document.asp?doc_id=1279807

Ive used the fixed point library successfully in quartus, but I ise has problems synthesizing the '93 compatible versions of the fixed point libraries. You cash also do fixed point representation just fine with signed and unsigned type, you just need to keep track of the integer/fraction separation as fixed point arithmatic it's just integer arithmatic.

Hi,
this link may help you
http://forums.xilinx.com/t5/DSP-and...ating-point-values-to-fixed-point/td-p/210721

@TrickyDicky @linam , thank you both for your input

I was on my way to draw a block diagram on how it should look when i came across this excelent link
https://surf-vhdl.com/how-to-implement-fir-filter-in-vhdl/

@linam I looked at that link i did not understand why floating point numbers need to be normalized before converting to fixed point ? , also won't that affect the filter because you are now using different coefficients ?

@TrickyDicky I came across one of your older posts https://www.edaboard.com/threads/203061/ , after looking at the fixed point library header at https://github.com/ctn-waterloo/nef-fpga/blob/master/contrib/fixed_pkg/fixed_pkg_c.vhd , i guess what you mean is that this package is only ment to work with "VHDL-93 supported compilers "

So my question would be did you try this on ISE ( XST) or on Vivado( i guess a new synthesis engin) ?

I was also wondering how we could keep the coefficients on a FPGA , do you need to manually instantiate a BlockRAM and keep it or would it be possible to inter storage
by using VHDL , what is the best for performance , if possible an example would be great

from the following code , what does the synthesizer which supports the fixed_point package do ? , does it insert additional logic to manage the binary point ? , but the adder synthesized would be the same as the interger one right ?

Thanks in advance

from the following code , what does the synthesizer which supports the fixed_point package do ? , does it insert additional logic to manage the binary point ? , but the adder synthesized would be the same as the integer one right ?

Click to expand...

If both fixed point numbers have same number of fractional bits, the package is only creating an implicit scaling factor, synthesizing regular integer math. Fixed point package can also enable additional features like saturation logic, very interesting for filters and other signal processing tasks. And it adjusts multiply results to the specified format, things that can be quite confusing when performed manually.

I don't understand by the way how floating point comes into play. You have real constants that are converted to fixed point constants without involving logic, but no floating point numbers.

The library you link to was written by David Bishop and was meant to allow '93 compilers access to code that was in the vhdl 2008 standard. When they were released, there was a version for each compiler as there were elements of the package that each compiler choked on. Ise was the worst with many features that were legal '93 syntax but it wouldn't compile. Ise had always had a terrible reputation for support. You'll have to check the project to see which compiler that code was written for, and you may have to modify it yourself to get it to compile if it's the quartus version.

All the fixed point library does is make it easier for the user to represent the code. The underlying logic will otherwise be identical to an implementation using only offset integers (probably using unsigned/singed types).

Coefficient storage will be a bram if there are a lot of coefficients, and you can infer such a thing from hdl code, as long as you follow the correct templates. Use has coding guidelines on how to do this.

Don't recent Xilinx tools provide support for 2008 ieee.fixed_pkg?

Ise does not. Vivado may do, I'm not sure. But the last I saw of vivado it still only supports a select set of 2008 features so the fixed_pkg from 2008 still cannot work. But they may include the pkg in the '93 form (like q16.0 does)

FvM said:

I don't understand by the way how floating point comes into play. You have real constants that are converted to fixed point constants without involving logic, but no floating point numbers.

Click to expand...

Hmm... , i was not talking about floating points ( at least i dont think so ) . in my sample code, as you mentioned i was just assigning fixed point values. whatever the value we assign what i understood is that the package makes sure that it fits in the range by rounding.

What i noticed is that these packages help with simulation, but underlining structures are the same for signed, unsigned, fixed , std_logic_vector. In the case of fixed point howerver i think there might be some logic to manage the decimal point

i was not talking about floating points ( at least i dont think so )

Click to expand...

Sorry for being unclear. linam posted a link about floating point to fixed point conversion, probably off-topic.