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W/L ratio of CMOS BASED circuits (or change of technology)

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simplsoft

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I am working on CMOS based circuit and I am stucked. The circuit has in total 30 NMOS and PMOS transistors. what if I decrease the lenght of all the 30 transistors from 180nm to 130nm. What will be the parameters that will be effected.

Can anyone tell me how to plot the transconductnace Vs frequency graph in Cadnce softeware of the overall circuit having 30 transistors?
 

Parameter number one: your database gets rejected because
you went under the foundry litho minimum.

Parameter two: at 130nm your gate oxide and a lot of secondary
device features are foinf to be different because you are on a
different flow, maybe even a different fab line.

Since you don't bother to say what kind of circuit, there's
no basis or reason to guess at what its parameter shifts might
be. If you enumerated these then maybe someone would
have guesses or even experience with such a migration.
 

simplsoft said:
I am working on CMOS based circuit and I am stucked. The circuit has in total 30 NMOS and PMOS transistors. what if I decrease the lenght of all the 30 transistors from 180nm to 130nm. What will be the parameters that will be effected.

Can anyone tell me how to plot the transconductnace Vs frequency graph in Cadnce softeware of the overall circuit having 30 transistors?
Click to expand...


I can say almost everything will change

1- If you have constant current which is produced by current sources with changing L, W/L ratio changes -> Id = k W/L (Vo) ^2 -> overdrive voltage changes and gm as well. lower L higher W/L and higher gm.

2- Ron of transistor changes. when you have lower L you will have lower Ron and Ro so your gain might decrease.
3- You will have higher bandwidth because your device capacitance deceases (C=WLCox)
4- Lower L means higher mismatch between transistor pair.
 

change of Technology not W/L ratio

I want to replicate a circuit having 30 transistors (NMOS+PMOS) with 180nm technology. But I dont have 180nm technology. I have 130nm technology parameter what if I keep the W/L ration of the circuit having 30 transistors (NMOS+PMOS) same and just change the technology instead of using 180nm, I use 130nm. that means the tranistor parameters will be different but I keep W/L ration same. Will there be some effect on the output of circuit? will it be a major effect or minor?
 

Ofcourse it will be a major effect. In new technology your mobility, Cox and lambda have been changed therefore, your current, bandwidth and gain will change. You have to redesign for new tech.
 

I am new in this field and I want to know How may I be knowing the mobility, bandwidth and gain.I have 130nm IBM technology in CADence software enviroment. I just go to its library and pick the 130nm technology FETs. From where will I be knowing its mobility.Do I have to calculate or it will be provided by the 130nm IBM technology.?

- - - Updated - - -

sorry I was asking of mobility, COX and lamda.
 

Presumably you would just optimize the circuit using the
new PDK models. Knowing surface mobility value does not
really help with that (besides which at short channels
stuff like velocity saturation is a big deal, mobility alone
fails to predict performance).

The bigger problems may be loss of headroom / dynamic
range, which could drive topology changes you didn't
really want to get into (if this is a "fab-port" paradigm,
I'd bet nobody plans on doing much work, despite this
almost never being true).
 

I have a circuit which I have attached. Its in 0.5um technology. what if I keep W/L ratio same and use 130nm technology. If I have tried this with 130nm but I am not getting the gain.
123.png
 

You cannot get the same gain. Because in lower technologies your Va (Early voltage) is lower and therefore, you will have lower output tesistance and low gain. For getting same gain you should increase L and gm.
 

At 130nm you don't have to make -every- transistor 130nm
long. What does the circuit do if you use the original W, L
values (aside from not being able to operate at the original
VDD)? How does PDK model lambda / Early voltage compare
(in simulation results, not in parameterization) for same-size
and same-bias FETs (bearing in mind that 130nm may also
have a lesser VT and maybe not even be fully "off" at low
Vgs, even zero)?

Moving to self-cascode styles in place of solo FETs can
be a simple-ish substitution especially when VT has gone
lower. A self-cascode of zero-VT or low-VT over regular
VT has been useful to me many times.
 

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