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Standard cell pin routing

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biju4u90

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Which metal layer is used for standard cell pins? Will all the pins be M1 or will it always be M2 or will it be a combination of M1 and M2 or can it be a higher metal layer like M3??
 

Depends on technology and std cell design. Usually M1 and M2, combined, are used for pins.
Larger macros like SRAMs will use M3 and above, but standard cells usually don't.
 
What about VDD and VSS pins of the standard cell?? Will they also be in M1 and M2 layers?
 

biju4u90 said:
What about VDD and VSS pins of the standard cell?? Will they also be in M1 and M2 layers?
Click to expand...

Yes and no. It is common for the cell to have VDD/VSS pins in M1 only, but then the user is obliged to draw a thick M2 on top of the M1 rail, and fill it with as many vias as possible.
 
So, in general, if I am having a 8 metal layer process, M8 and M7 will be used for power routing, M6 and M5 for clock routing, M1 and M2 for standard cell pins and power and their routing. What about M3 and M4 in this case?? Will they be used for routing power supply, clock and signal nets?? Or is it like some layers are reserved for some nets only? Will M6 and M5 be used for power routing also or will they be used only for clock routing?
 

biju4u90 said:
So, in general, if I am having a 8 metal layer process, M8 and M7 will be used for power routing, M6 and M5 for clock routing, M1 and M2 for standard cell pins and power and their routing. What about M3 and M4 in this case?? Will they be used for routing power supply, clock and signal nets?? Or is it like some layers are reserved for some nets only? Will M6 and M5 be used for power routing also or will they be used only for clock routing?
Click to expand...

M3 is tricky, it will be used for both signal routing as well as power routing (assuming you have two power grids). M5 and M6 will be used for clock but also signal, especially big busses. It is common to do clock routing with 2W2S (double width double spacing), so whatever is left can be used for signal routing.
 

In such a situation, will clock be routed in M3 also or in M1 and M2 also??
 

biju4u90 said:
In such a situation, will clock be routed in M3 also or in M1 and M2 also??
Click to expand...

Please understand that because a metal layer was assigned to clock, or to power, it doesn't mean it is forbidden to do signal routing with it. It's just a preference. Of course clock will use M3 and below, otherwise how would it reach the flops?
 
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